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Anand Bulusu

Anand Bulusu

Professor

anand.bulusu@ece.iitr.ac.in
01332-246588
Resume

CMOS Digital Circuits, Timing models and design of near threshold voltage circuits, VLSI Devices, Novel device/circuit co-design methodologies, MIxed-Signal Design, Low Voltage CMOS Circuit Design and Modeling
From To Designation Organisation
2006 2007 Sr. Research Engineer IIT Bombay
2007 2008 Sr. Design Engineeer Freescale Semiconductor India (Presently NXP Semiconductrs)
2008 2014 Assistant Professor IIT Roorkee
2014 Present Associate Professor IIT Roorkee
Degree Subject University Year Studied
Ph.D Microelectronics IIT Bombay 2006
From To Designation Organisation Level
2013 On going Faculty Advisor IEEE CAS Student Chapter, IIT Roorkee
2014 On going Branch Counsellor IEEE Student Branch
Scheme Sponsoring Agency Other Faculties Year Sponsored
Development and Efficient Characterization of FB and DT CMOS PDSOI Standard Cell Libraries DST (AMT) 2019
Negative capacitance fet (NCFET): fabrication/modeling/simulation for design of digital circuits DST Nano Mission 2019
An Energy Efficient IOT Processor using an Optimized Near-Threshold Voltage Standard Cell Library IMPRINT-2 (SERB) 2019
A robust and scalable VLSI test methodology for high performance CMOS designs considering spatial an Semiconductor Research Corporation 2018
ICT Academy DIETY 2016
Chips to Systems Design (SMDP) DIETY 2015
Robust Methodology for Nanoscale VLSI Circuit Design Considering Layout Dependent Variatiations DST 2013
Nanoscale FinFET Device and Circuit Design Methodology DST 2009
Membership Details
IEEE Circuits and Systems Society, Member
IEEE Electron Device Society, Member
IEEE Solid State Circuits Society, Member
Title Course Code Course Semester
Fundamentals of Microelectronics EC 344 UG Spring
Analog Circuits EC 205 UG Autumn
Digital VLSI Circuit Design EC 573 PG + UG Spring
Semiconductor Devices EC 142 U.G. Spring
Analog VLSI Circuit Design EC 581 PG Spring
Automatic Control Systems EC 222 UG Spring
Electronic Network Theory EC 291 UG Autumn
Fundamentals of Electronics EC 102 U.G. Spring
Topic Scholar Name Status of PhD Registration Year
FinFET Device-Circuit interaction (Analog Domain) Shashank Bancchor O 2015
NC-TunnelFET Devie-Circuit Interaction Khoiram Johnson O 2019
NCFET Device-Circuit Interaction Amit Bahera O 2019
Variation Aware Timing Models of CMOS Circuits Lomash Acharya O 2019
Near Threshold Standard Cell Design and Characterization Mahipal D. O 2019
Circuit design for in-memory computing Dinesh Kushwaha O 2018
Tunnel FET Device-Circuit Interaction Abhishek Acharya A 2015
CMOS PLL Design Neeraj Mishra O 2016
Low Voltage CMOS VCO Design Lalit Dani O 2015
Near Threshold CMOS Digital Circuit Design and Analysis Inder Chaudhary O 2014
FinFET device-circuit interaction in low-voltage domain Sarita Yadav O 2016
Mechanical Stress Aware Nanoscale VLSI Circuit Design Methodologies Arvind Sharma A 2013
Radiation hard data converters Ashutosh Yadav O 2019
Modeling of FinFET device parasitics Archana Pandey A 2012
TunnelFET device-circuit co-design Menaka A 2010
Device-circuit co-design of Silicon Nanowire transistor Satish Maheshwaram A 2010
Performance models for nanoscale VLSI circuits Baljit Kaur A 2010
Robust circuit design methodology for nanoscale VLSI technologies Naushad Alam A 2009
Course Name Sponsored By Date Participated
Design Issues in Nanoscale VLSI Circuits and Systems QIP 10-Jun
Title Place Date Delivered
FinFET Device Circuit Co-Design: Issues and Challenges IEEE VLSI Design Conference 2015, Bangalore 04.01.2015
Nanoscale VLSI Circuit Design: Timing Issues and Solutions NITTTR, Chandigarh 09.10.2016
Topic Organisation Level
Process variation aware Standard Cell extraction Freescale Semiconductor India Pvt. Ltd. PG
Tunnel FET Device Modeling ST Microelectronics PG
CMOS VCO Design ST Microelectronics PG
High Speed Circuits Global Foundries PG
SRAM Yield Analysis ARM NOIDA PHD

Selected Publications in International Journals:

 

  1. Neeraj Mishra, Lalit M Dani, Kunal Sanvaniya, S. Dasgupta, S.Chakraborty and Anand Bulusu, "Design and Realization of High-Speed Low-Noise Multi-loop Skew-based ROs Optimized for Even/Odd Multi-Phase Signals," Accepted for publication in IEEE Transactons on Circuits and Systems II: Express Briefs.
  2. Chaudhry I. Kumar and Bulusu Anand, "A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design, Accepted for pubilcation in IEEE Transactions on Device and Material Reliability.
  3. Lalit Dani, N. Mishra, A. Sharma, Bulusu Anand, “Variation Aware Prediction of Circuit Performance in Near-threshold Regime using Supply Independent Transition Threshold Points,” Accepted for publication in IEEE Transactions on Electron Devices.
  4. C. I. Kumar and B. Anand, "A Highly Reliable and Energy Efficient Triple-Node-Upset Tolerant Latch Design", Accepted for publication in IEEE Transactions on Nuclear Science.
  5. Abhishek Acharya, A. B. Solanki, S. Glass, Q. T. Zhao, and Bulusu Anand, "Impact of Gate-Source Overlap on the Device/ Circuit Analog Performance of Line TFETs," Accepted for publication in IEEE TED.
  6. Shashank Banchhor, Kintada Dinesh Kumar, Ashish Dwivedi and Bulusu Anand, “A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits,” Accepted for publication in IEEE TED.
  7. Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal,H.S. Jatana, and Anand Bulusu, "A Physics based Variability Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches," Accepted for publication in IEEE Transactions on VLSI.
  8. Chaudhry Indra Kumar and Bulusu Anand, "High Performance Energy Efficient Radiation Hardened Latch for Low Voltage Applications,” Elsevier VLSI Journal of Integration, Accepted for publication.
  9. Chaudhry Indra Kumar, Arvind K. Sharma, Rajendra Partap, Anand Bulusu, “An energy-efficient variation aware self-correcting latch,” Elsevier Microelectronics Journal, pp. 67 – 78, February 2019.
  10. Chaudhry Indra Kumar and Bulusu Anand, “Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell,” IET Electronics Letters, pp. 1423 – 1424, December 2018.
  11. Arvind Sharma, Naushad Alam and Anand Bulusu, “Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design Techniques,” IEEE Transactions on Electron Devices, pp. 2413 – 2421, June 2018.
  12. Abhishek Acharya, Abhishek Solanki, Sudeb Dasgupta and Bulusu Anand, “Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective,” IEEE Transactions on Electron Devices, Volume: 65, Issue: 1, Jan. 2018.
  13. Om Prakash , Satish Maheshwaram,Mohit Sharma Anand Bulusu , Sanjeev K. Manhas, “Performance and Variability Analysis of SiNW 6T-SRAM Cell using Compact Model with Parasitics,” IEEE Transactions on Nanotechnology , Volume: 16, Issue: 6, Nov. 2017.
  14. Om Prakash, Swen Beniwal, Satish Maheshwaram, Anand Bulusu, Navab Singh, and S. K. Manhas, “Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 2, JUNE 2017.
  15. Arvind Sharma, Naushad Alam and Anand Bulusu, “Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design,” IEEE Transactions on Electron Devices, 2017.
  16. Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “A Novel VDSAT Extraction Method for Tunnel FETs and Its Implication on Analog Design,” IEEE Transactions on Electron Devices, pp. 629-623, February 2017.
  17. Arvind Sharma, Naushad Alam, Sudeb Dasgupta, Bulusu Anand, “Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits”, IEEE Transactions on Electron Devices, PP, no. 99, 2016. 
  18.  Baljit Kaur, Arvind Sharma, Naushad Alam, Sanjeev K. Manhas, Bulusu Anand, “A Variation Aware Timing Model for a 2-Input NAND Gate and Its Use in Sub-65nm CMOS Standard Cell Characterization”, Microelectronics Journal (Elsevier), vol. 53, pp. 45-55, 2016.
  19. Archana Pandey; Harsh Kumar; S. K. Manhas; Sudeb Dasgupta; Bulusu Anand , “Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and significance” , IEEE Transactions on Electron Devices, pp. 1392-1396, march 2016.
  20. Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand, “Efficient ECSM characterization considering voltage, temperature and mechanical stress variability,” Accepted for publication in IEEE Transactions on Circuits and Systems – I, October 2014.
  21. Gaurav Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Novel Design Methodology Using Lext Sizing in Nanowire CMOS Logic” IEEE Transactions on Nanotechnology, pp. 650-658, July 2014.
  22.  Naushad Alam, Bulusu Anand and Sudeb Dasgupta, “An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design,” IEEE Transactions on Circuits and Systems -I, pp. 1714-1726, June 2014.
  23. Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta,  Bulusu Anand, “Effect of Load Capacitance and Input Transition Time on Underlap FinFET Capacitance,” IEEE Transactions on Electron Devices, pp. 30-36, January 2014.
  24. Ashwani Kumar, Vishvendra Kumar, Bulusu Anand, S. Manhas, “Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance,” IEEE Transactions on Nanotechnology, pp. 16-22, January 2014.
  25. Menka, Bulusu Anand and Dasgupta S., “Two Dimensional Analytical Modeling for Asymmetric 3T and 4T Double Gate Tunnel FET in Subthreshold Region: Potential and Electric Field”, Elsevier Microelectronics Journal, pp. 1251-1259, December 2013.
  26. S. Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, “Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis,” IEEE Transactions on Electron Devices, vol. 60, no. 9, pp. 2943-2950, September 2013.
  27. N. Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Variable Taper CMOS Buffer Design", Elsevier Microelectronics Reliability, vol. 53, Issue 5, pp. 718-724, May 2013.
  28. N. Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress on CMOS Buffer Design using Multi-Fingered Devices", Elsevier Microelectronics Reliability, vol. 53, Issue 3, pp. 379-385, March 2013.
  29. N. Alam, B. Anand, and S. Dasgupta, "Gate-Pitch Optimization for Circuit Design using Strain-Engineered Multi-Finger Gate Structures", IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3120-3123, November 2012.
  30. Gaurav Kaushal, S. Manhas, S. Maheshwaram, S. Dasgupta, A. Bulusu and N. Singh, “Tuning source/drain extension profile in current matching in nanowire CMOS logic,” IEEE Transactions in Nanotechnology, vol. 11, no. 5, pp. 1033-1035, September 2012.
  31. Satish Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform,"  IEEE Electron Device Lettersvol.33, no. 7, pp.934-936, July 2012.
  32. Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab Singh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS,” IEEE Electron Device Letters, pp. 1011-1013, August 2011.
  33. Pradeep Kumar Chawda, B. Anand, V. Ramgopal Rao, “Optimum Body Bias constraints for leakage reduction in high-K Complementary Metal Oxide Semiconductor Circuits,” Japanese Journal of Applied Physics (JJAP), May 2009.
  34. Bulusu Anand, M. P. Desai, and V. Ramgopal Rao, "Silicon Film Thickness Optimization for SOI-DTMOS from Circuit Performance considerations", IEEE Electron Device Letters, pp. 436-438, June 2004.
  35. P. Sivaram, B. Anand, M. P. Desai, “Silicon film thickness considerations for SOI-DTMOS,” IEEE Electron Device Letters, pp. 276-278, May 2002.

Selected Publications in International Conferences:

  1. Lalit M. Dani, Neeraj Mishra and Anand Bulusu, “MOS Varactor RO architectures in Near Threshold Regime using Forward Body Biasing techniques,” VLSI Design Conference, January 2019, Delhi.
  2. Lalit M. Dani, N. Mishra, S.K. Banchhor, S. Miryala, A. Doneria, Bulusu Anand, “Design and Characterization of Bulk Driven MOS Varactor Based VCO at Near Threshold Regime,” IEEE-S3S, San Francisco, October 2018.
  3. R. Chawla, S. Yadav, A. Sharma, B. Kaur, R. Pratap and Bulusu Anand, “TSV Induced Stress Model and Its Application in Delay Estimation,” IEEE-S3S, San Francisco, October 2018.
  4. C. Inder Kumar and Bulusu Anand “Design and Analysis of Energy-Efficient Self-Correcting Latches Considering Metastability,” IEEE PRIME, July 2018, Prague.
  5. A. Sharma, N. Alam, A. Bulusu, “UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective,” IEEE PRIME, July 2018, Prague.
  6. Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu, “A Modified Method of Logical Effort for FinFET Circuits considering of Fin-Extension Efforts,” Proceedings of IEEE ISQED-2018, Santa Clara.
  7. Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, "Impact of Device Design Parameters on VDSAT and Analog Performance of TFETs," Presented at IEEE Silicon Nanoelectronics Workshop 2017, Japan.
  8. Chaudhry Indra Kumar, A. Sharma, S. Miryala, Bulusu Anand, "A novel energy-efficient self-correcting methodology employing INWE," IEEE SMACD, 2016, Lisbon.
  9. Sayyaparaju Sagar Varma, A. Sharma, Bulusu Anand, "An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis," IEEE SMACD, 2016, Lisbon.
  10. Archana Pandey, Harsh Kumar, Praanshu Goyal, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand “FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay” , IEEE VLSI Design, 2016, Kolkata.
  11. Arvind Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, and Bulusu Anand, "Pre-layout Estimation of Performance and Design of Basic Analog Circuits in Stress Enabled Technologies" in IEEE VDAT, 2015.
  12. Yogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, and Bulusu Anand, "Timing Model for Two Stage Buffer and Its Application in ECSM Characterization", in IEEE VDAT, 2015.
  13.  A. Sharma, Y. Sharma, S. Dasgupta, and B. Anand, “Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model”, IEEE ISQED-2015.
  14. Parmanand Singh,V. Asthana, R. Sithanandam, A. Bulusu, S. Dasgupta, “Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor,” IEEE VLSI Design, 2014.
  15. Bijay Kumar Dalai, A. Bulusu, N. Kannan and Arvind Kumar Sharma, "An Empirical Delta Delay Model for Highly Scaled CMOS Inverter Considering Well Proximity Effect," VDAT 2014.
  16. Saurabh K. Nema, M. SaiKiran, P. Singh, Archana Pandey, S. K. Manhas, A. K. Saxena, Anand Bulusu, “Improved Underlap FinFET with Asymmetric Spacer Permittivities,” Accepted in IWPSD 2013.
  17. S. Maheshwaram, S.K. Manhas, G. Kaushal, and B. Anand, “Vertical Nanowire MOSFET Parasitic Resistance Modeling,” in Proc. IEEE EDSSC 2013, Hong Kong.
  18. Menka, Bulusu Anand and Dasgupta S., “A TCAD approach to evaluate channel electrondensity of double gate symmetric n-tunnel FET”, INDICON 2012, pp:577-581.
  19. Baljit Kaur, S. Miryala, S. K. Manhas and Bulusu Anand, “An Efficient Method for ECSM Characterization of CMOS Inverter in Nanometer Range Technologies,” Accepted in IEEE International Symposium on Quality Electronic Design (ISQED) 2013.
  20. Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, Bulusu Anand, “Underlap FinFET Capacitance: Impact of Input Transition Time and Output Load” IEEE International Nanoelectronics Conference (INEC) 2013.
  21. N. Alam, B. Anand, and S. Dasgupta, “Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance”, in IEEE ISQED, 2012, pp. 717-720.
  22. N. Alam, B. Anand, and S. Dasgupta, “Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance", in VDAT 2012, pp. 357-359.
  23. N. Alam, S. Dasgupta, and B. Anand “Impact of process-induced mechanical stress on multi-fingered device performance”, in Proc. IWPSD, 2011.
  24. Arnab Kumar Biswas, Anand Bulusu and Sudeb Dasgupta, “A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz,” Proceedings of IEEE ISVLSI 2011.
  25. Sandeep Miryala, Baljit Kaur, Bulusu Anand and Sanjeev Manhas, "Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model," Proceedings of IEEE ISQED 2011.
  26. Saurabh Nema, Mayank Srivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, "A Novel Scaling Strategy for Underlap FinFETs," ICCCD 2010, IIT Kharagpur.
  27. Bulusu Anand, V. Ramgopal Rao and M. P. Desai, "Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics,” Accepted in VLSI-DAT, 2007.
  28. Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, "Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits", Proceedings of 35th International Conference on Solid State Devices and Materials (SSDM 2004), pp. 434-435, Tokyo, Japan, September 15-17, 2004.
  29. Sushant Suryagandh, B. Anand, M. P. Desai and V. Ramgopal Rao, “Dynamic Threshold Voltage CMOS (DTMOS) for Future Low Power Sub-1V Applications," Proceedings of 10th International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 655-658, December 1999, New Delhi.

IP:

  1. Bulusu Anand, Shivananda Reddy, Surya Veeraraghavan, “A Method to Find Sensitivity of Standard Cells to Process/Model Changes,” Defensive Publication of Freescale Semiconductor Inc., June 2008, http://www.priorartdatabase.com/IPCOM/000172383/
  2. S. K. Manhas, S. Nema, A. Bulusu, “A method of fabricating dual/asymmetric dielectric constant (dual-K) spacers in MOSFET,” application no. CINIITR000100017, 2012 (Provisional Indian Patent).


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