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Sudeb Dasgupta

Sudeb Dasgupta

Professor

sudeb.dasgupta@ece.iitr.ac.in
01332-285666
My Website

  • Ultra Low Power, Adiabatic Logic for Portable Applications
  • Low Power Application, Subthreshold Logic Design
  • Radiation Effects on ICs, Design and Development of 6T FinFET Based Rad Hard SRAM Cell
  • Novel Semiconductor Devices, FinFETs, PDSOI, FDSOI
  • Nanoelectronics, Semiconductor Device Modelling
From To Designation Organisation
2000 2005 Lecturer Indian School of Mines, Dhanbad
2005 2006 Assistant Professor Indian School of Mines, Dhanbad
2006 Present Assistant Professor Indian Institute of Technology, Roorkee
1998 2000 Technical Committee Member VISION-2000
2003 Present Reviewer VLSI Design and Test Symposium
2003 Reviewer Semiconductor Science and Technology IOP
2004 Reviewer IETE J. of Research
2004 Present Reviewer International VLSI Design Conference
2006 Reviewer International Journal of Electronics TAF
2006 Present Reviewer IEEE Transactions on Nanotechnology
2007 Reviewer IEEE Transactions on VLSI
Award Institute Year Awarded
Expert Member The Global Open University, The Netherlands 2001
Senior Research Fellow Department of Science and Technology, GOI 1997
Marquis's Who's Who in Science in Engineering, USA Marquis 2006
Best Paper Award IWPSD-2005 2005
Technical Commitee Member International Conference on Micro-to-Nano 2006
Erasmus Mundus Fellow Politechnico di torino 2010
IUSSTF Fellow University of Wisconsin, Madison, USA 2011
DAAD Fellow TU, Dresden, Deutschland 2013
Degree Subject University Year Studied
Ph.D Electronics Engineering Banaras Hindu University 2000
From To Designation Organisation Level
2000 2005 Member, Tender Adisory Committee Indian School of Mines, Dhanbad
2001 2003 Warden Indian School of Mines, Dhanbad
2002 2005 Member, time-Table Commitee Indian School of Mines, Dhanbad
2002 2003 Member, Academic Council Indian School of Mines, Dhanbad
2003 2005 Member, Departmental Research Commitee Indian School of Mines, Dhanbad
2003 2004 Member Secretary, Board of Courses and Studies Indian School of Mines, Dhanbad
2003 2005 Member, Research Council Indian School of Mines, Dhanbad
2005 2005 Member, Institute Web-site Committee Indian School of Mines, Dhanbad
2006 O.C. Purchase IIT Roorkee
2006 2011 O.C. VLSI Design Lab IIT Roorkee
2006 Present Co-Coordinator IIT-R SMDP For VLSI Design and Related S/W - Phase-II
2006 Present O.C. Solid State Devices (R&D) Lab
2007 Present Member DUGC, E&CE
2015 2017 Chairman, DAPC IIT Roorkee
Scheme Sponsoring Agency Other Faculties Year Sponsored
Modelling and Simulation of Nanoscale MOSFET for their use in future VLSI/ULSI schemes Ministry of Human Resources and Development, GOI 2003
SMDP-C2SD DEITY 2015
SMDP-II Ministry of Information and Communication Technology, Government of india 2005
Membership Details
EDS, Member
ISTE, Member
Institute of Nanotechnology, Associate Member
IEEE, Member
Title Course Code Course Semester
Digital Electronics EC-203 B.Tech-II EC& CSE Autumn
Electronic Network Theory EC-291 B.Tech II Year Spring
Lab-II EC-650 P.G.(including Pre Phd Course) Spring
Semiconductor Device Models for Circuit Simulation EC-502 P.G.(including Pre Phd Course) Autumn
Semiconductor Device Lab EC-550 P.G.(including Pre Phd Course) Autumn
Analog VLSI Design EC-558 P.G.(including Pre Phd Course) Autumn
Semiconductor LAB EC-351 U.G. Autumn
Digital VLSI Design EC-557 P.G.(including Pre Phd Course) Spring
VLSI Technology EC-555 P.G.(including Pre Phd Course) Spring
Topic Scholar Name Status of PhD Registration Year
Modelling and Simulation of Nanoscale Metal Oxide Semiconductor Feild Effect Transistors A. Annada Prasad Sarab A
Analytical Modeling of Nanoscale MGDG MOSFET and its Application to SRAM S. K. Vishvakarma A
Analytical Modeling of Double Gate FinFET and its Applications to SRAM Cell Design Balwinder Raj A
Sub threshold Logic Design for Low Power Applications Ramesh Vaddi A
Radiation Effect on SOI based devices and circuits Surendra Rathod A
Adiabatic Circuits Jitendra Kanungo A
Silicon Nanowires Gaurav Kaushal A
FinFET Design Issues Ashutosh Nandi A
Robust Nanoscale Circuit Studies Naushad Alam A
Variability studies in decanano FiNFET based circuits and systems Menka A
FinFETs for RF Applications Savitesh Sharma A
Course Name Sponsored By Date Participated
Instruction Enhancement Programme IIT-Kanpur/ SMDP-II 03.07.2006
Title of Project Name of Student
DESIGN OF LOW POWER DIGITAL FILTER Kshipra Jain, Sonal Tyagi and Sujit Kumar
A CMOS Phase Frequency Detector for High Speed PLL with Linear Phase Transfer Characteristics Mohammed Khadar
Compact Analytical Modelling of Gate Leakage Current with S/D overlap for Nanoscale N-MOSFET Ashwani Rana
Designing of ALU for a 16-bit RISC Microprocessor Architecture Avnish Varshney
Scholar Name Interest
Annada Sarab Modeling and Simulation of Quantum Effect in Nanoscale MOSFET
Balwinder Raj FinFet Device Modeling and Nanoscale Memory Design
V. Ramesh Low Power VLSI Design
Surendra Rathod Study of Radiation Effects on SOI based devices and circuit
Jitendra Kanungo Adiabatic Logic Design
Ashutosh Nandi Dual-k FinFET based Analog Design
Pankaj Pal SRAM memory design enhancements using sub 22 nm devices
Institute Visited Purpose of Visit Visit Date
UNIK, Norway Joint Research 15-07-2009
Politechnico Di Torini, Italy Research, EM Fellow 20-05-2010
University of Wisconsin-Madison Indo US Fellowships, Collaborative Research 20-05-2011
Conference Name Sponsored By Date
STEP-VHDL STEP/IITR

Semi-numerical Modelling of an n-channel Irradiated MOSFET

By: S.Dasgupta and P.Chakrabarti

Published in: International Journal of Electronics Vol: 88 (Pg 301-313) Date: 2001

Influence of Ionising Radiation on CMOS Inverters

By: S.Dasgupta, R.K. Chauhan and P. Chakrabarti

Published in: Microelectronics Journal (Elsevier) Vol: 32 (Pg 615-620) Date: 2001

Ionising Radiation effects in an Ion-Implanted MOSFET: A Two-Dimensional Analytical Study

By: S.Dasgupta, R.K. chauhan, G. Singh and P. Chakrabarti

Published in: International Journal of Electronics Vol: 89 (Pg 277-288) Date: 2002

A pseudo-two-dimensional model of an n-channel MOSFET under the influence of Ionising Radiation

By: S.Dasgupta, R.K. Chauhan and P. Chakrabarti

Published in: Semiconductor Science and Technology (IOP) Vol: 17 (Pg 961-968) Date: 2002

Two-Dimensional Numerical Modeling of a deep sub-micron Irradiated MOSFET to extract its Global Char

By: S.Dasgupta

Published in: Semiconductor Sceince and Technology (IOP) Vol: 18 (Pg 124-132) Date: 2003

Self-consistent Solution of Two-dimensional Poisson Equation and Schrodinger Wave Equation for Nano-

By: Deepesh Jain and S.Dasgupta

Published in: Journal of Nanoscience and Nanotechnology (APS) Date: 2004

Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

By: Deepanjan Datta, A.A.P.Sarab and S.Dasgupta

Published in: Journal of Computational and Theoretical Nanoscience Vol: 3 (Pg 414-422) Date: 2005

Study of the Leakage Current in Novel Nanoscale Device Architecture depending on Doping Profile

By: D.Datta and S.Dasgupta

Published in: Journal of Computational and Theoretical Nanoscience Vol: In press Date: 2006

Self-Consistent Solutions of 2D-Poisson and Schrodinger Wave Equations for a Gaussian Doped 50 nm MO

By: A. Agrawal and S.Dasgupta

Published in: Journal of Computational and Theoretical Nanoscience Vol: 3 (Pg 101-109) Date: 2006

Design and Development of Ultra Low Power MOS based VLSI Architecture

By: Deepanjan Datta and S.Dasgupta

Published in: Journal of Computational and Teoretical Nanoscience (APSBS) Vol: 3 (Pg 01-11) Date: 2006

Two-Dimensional Analytical Modeling of Gaussian Doped Nano-scale Double-gate MOSFET

By: D.Datta, A.A.P.Sarab and S.Dasgupta

Published in: Microelectronics Journal (Elsevier) Vol: 37 (Pg 537-545) Date: 2006 (online)

Nanoscale Device Architecture to Reduce Leakage Current through QM Modelling Schemes in current VLSI Technology Node

By: A.A.P.Sarab, Deepanjan Datta and S.Dasgupta

Published in: Virtual Journal of Nanoscale Science and Technology Vol: 00 (Pg 1384-1397) Date: 2006

Novel Design Technique to reduce off state power dissipation in MOS based devices: A QM Study

By: Deepanjan Datta, Samiran Gangulay, A.A.P.Sarab and S.Dasgupta

Published in: Journal of Vacuum Science and Technology-B Vol: 24 (Pg 1384-1397) Date: 2006

Novel Nanoscale Device architecture to reduce Leakage Currents in Logic Circuits: A Quantum-Mechanic

By: D.Datta, S. Ganguly, A.A.P.Sarab and S.Dasgupta

Published in: Semiconductor Science and Technology (IOP) Vol: 21 (Pg 397-408) Date: 2006

Modeling and Simulation of the Nanoscale Triple-Gate

By: Deepanjan Dutta, A.A.P.Sarab and S.Dasgupta

Published in: Journal of Nanoscience and Optoelectronics Vol: 01 (Pg 1-14) Date: 2006

Low Band-to-Band Tunnelling and Gate Tunnelling Current in Novel Nanoscale Double-Gate Architecture: Simulations and Investigation

By: Deepanjan Dutta, samiran Ganguly and S.Dasgupta

Published in: Nanotechnology (IOP) Vol: 18 (Pg -) Date: 2007

Analytic Modeling of Non-Uniform Graded Dopant Profile of Polysilicon Gate in Gate Tunelling Current for N-MOSFET in Nanoscale Regime

By: Ashwani Kumar and S.Dasgupta

Published in: Journal of Computational and Theoretical Nanoscience Vol: 4 (Pg 179-185) Date: 2007

Unified Compact Modelling of a Gate Tunneling current considering Image Forge Barrier Lowering for nanoscale N-MOSFET

By: Ashwani Kumar and S.Dasgupta

Published in: Journal of Computational and Theoretical Nanoscience Vol: 4 (Pg 482-487) Date: 2007

Analysis and Evaluation of Output characteristics of Gaussian doped Nanoscale MOSFET using Green's

By: Ritambhar Roy and S.Dasgupta

Published in: Journal of Computational and Theoretical Nanoscience Vol: 3 (Pg 811-817) Date: 2006

Quantum Mechanical Treatment for the reduction of various leakage components in novel nanocscale MOS

By: Deepanjan Datta, A.A.P.Sarab and s.Dasgupta

Published in: Journal of Nanoscience and Optoelectronics Vol: 01 (Pg 237-250) Date: 2006

Evaluation of Threshold Voltage for 30 nm Symmetric Double Gate (SDG) MOSFET and it’s Variation with Process Parameters

By: S. K. Vishvakarma, B. Raj, A. K. Saxena, Rahul Singh, Chinmaya R. Panda and S. Dasgupta

Published in: Journal of Computational and Theoretical Nanosciences , American Scientific Publishers (ASP) Vol: in press (Pg Accepted) Date: 0/0/0000

Two Dimensional Analytical Potential Modeling of Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra Thin Body (UTB)

By: S. K. Vishvakarma, Vinit Agrawal, B. Raj, S. Dasgupta, A. K. Saxena

Published in: Journal of Computational and Theoretical Nanoscience Vol: 4 (Pg 1144-1148) Date: Sept. 2007

Modeling of Inversion Charge Density in Nanoscale Symmetric Double Gate (SDG) MOSFET: An analytical Approach

By: S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta

Published in: Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers (ASP) Vol: 2 (Pg in press) Date: 2007

Total Citations
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