Analog and Mixed Signal Integrated Circuit Design, Data converter design for Instrumentation applications and Wireless Transceivers, RF CMOS IC design
From |
To |
Designation |
Organisation |
Jan-2022 |
Present |
Assistant Professor |
Indian Institute of Technology Roorkee |
July-2021 |
Dec-2021 |
Senior Project Officer |
Industrial Consultancy and Sponsored Research, IIT Madras |
May-2019 |
June-2021 |
Project Officer |
Industrial Consultancy and Sponsored Research, IIT Madras |
Jan-2014 |
June-2014 |
Project Associate |
Industrial Consultancy and Sponsored Research, IIT Madras |
July-2011 |
Dec-2013 |
Analog Design Engineer |
Analog Devices India Private Ltd., Bangalore |
Degree |
Subject |
University |
Year Studied |
Doctor of Philosophy |
Analog and Mixed Signal Integrated Circuit Design |
Indian Institute of Technology Madras |
2021 |
Master of Technology |
VLSI Design Tools and Technology |
Indian Institute of Technology Delhi |
2011 |
Bachelor of Engineering |
Electronics and Communication Engineering |
Anna University, Chennai |
2009 |
Membership Details |
IEEE Member |
Title |
Course Code |
Course |
Semester |
VLSI Mixed Signal Circuits |
ECN-584 |
M. Tech |
Jan-May 2022 |
Journal Publications
- S. Pavan and S. Manivannan, "Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2021.3121418.
- S. Manivannan and S. Pavan, "A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth," in IEEE Solid-State Circuits Letters, vol. 4, pp. 92-95, 2021, doi: 10.1109/LSSC.2021.3071965.
- S. Manivannan and S. Pavan, "Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3778-3789, Nov. 2020, doi: 10.1109/TCSI.2020.3013006.
- S. Manivannan and S. Pavan, "Degradation of Alias Rejection in Continuous-Time Delta–Sigma Modulators by Weak Loop-Filter Nonlinearities," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3207-3215, Oct. 2018, doi: 10.1109/TCSI.2018.2826443.
Conference Publications
- S. Manivannan and S. Pavan, "A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR," 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, pp. 1-4, doi: 10.1109/CICC.2018.8357089.
- S. Manivannan and S. Pavan, "Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-5, doi: 10.1109/ISCAS.2019.8702763.S. Kumar and S. Chatterjee, "A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time Delta Sigma Modulator for Audio Applications," 2012 25th International Conference on VLSI Design, 2012, pp. 51-56, doi: 10.1109/VLSID.2012.45.