- Darshak Bhatt
- Anand Bulusu
- Ajit K Chaturvedi
- Bishnu Prasad Das
- Avirup Dasgupta
- Sudeb Dasgupta
- Arnab Datta
- Devesh Dwivedi
- Debashis Ghosh
- Anshul Jaiswal
- MV Kartikeyan
- Brajesh Kumar Kaushik
- Brijesh Kumar
- Saurabh Khanna
- Dheeraj Kumar
- Debidas Kundu
- Sanjeev Manhas
- Sparsh Mittal
- Akhilesh Mohan
- Rajib Kumar Panigrahi
- Vinod Pankajakshan
- Nagendra P. Pathak
- Amalendu Patnaik
- Vishvendra Singh Poonia
- Pyari Mohan Pradhan
- Tanmoy Pramanik
- Karun Rawat
- Meenakshi Rawat
- Sourajeet Roy
- Abhay Kumar Sah
- Biplab Sarkar
- Ekant Sharma
- Dharmendra Singh
- Anshul Tyagi
Bishnu Prasad Das
|2012||2013||Post Doctoral Researcher||CMU, Pittsburgh, USA|
|2009||2012||Post Doctoral Researcher||Kyoto University, Japan|
|Young Faculty Research Fellowship (YFRF)||Ministry of Electronics & Information Technology (MeitY), Government of India||2018|
|Ph.D.||Electronics Design & Technology||IISc, Bangalore||2009|
|Scheme||Sponsoring Agency||Other Faculties||Year Sponsored|
|Design and on-chip characterization of standard cell library||FIG||2015|
|Design of Voltage-Scalable and Process Variation Tolerant Standard Cell Library||SERB||2016|
|SMDP C2SD (Chips to Systems Design)||MEITY||2015|
|IEEE Senior Member|
|Analog VLSI Circuit Design||ECN-581||M.Tech., B.Tech IV, Ph.D||Autumn|
|VLSI Physical Design||ECN-591||M.Tech., B.Tech IV, Ph.D||Spring|
|Digital System Design||ECN-578||M.Tech., B.Tech IV, Ph.D||Autumn|
|IC Application Laboratory||ECN-351||B.Tech III||Autumn|
|Digital Electronic Circuits Laboratory||ECN-252||B.Tech II||Spring|
|Microelectronic Devices,Technology and Circuits||ECN-341||B.Tech III||Autumn|
|Training and Seminar||EC-491||B.Tech IV||Autumn|
|DIGITAL LOGIC DESIGN||ECN-104||BTech (CSE)||Spring|
|Digital Logic Design||ECN-104||BTech (CSE)||Spring|
|Topic||Scholar Name||Status of PhD||Registration Year|
|Resilient Circuit Design||Sannena Govinda||A||2014|
|Sub-threshold Standard Cell Design||Priyamvada Sharma||A||2014|
|On-chip Process Variation Measurement||Poorvi Jain||A||2015|
|Memory Design||Prasanna Kumar Saragada||O||2017|
|DSP architectures||Anu Verma||O||2018|
|Soil Sensors||Aranya Gupta||O||2020|
|Memory Design||Amandeep Singh||O||2020|
|Ultra-low power circuit design||Anant Kumar Singh||O||2021|
|PLL Design||Anshul Verma||O||2019|
P1. Bharadwaj Amrutur and Bishnu Prasad Das, “Gate Delay Measurement Circuit and Method of Determining a Delay of a Logic Gate” US patent No. 8,224,604 B1 and date of Patent July 17, 2012.
P2. Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan, “Testing integrated circuits during split fabrication,” Application No: PCT/US2015/012220, Publication no: WO2015160405 A3, Publication date, Dec 10, 2015.
J11. Priyamvada Sharma and Bishnu Prasad Das, "Design and Analysis of Leakage-Induced False Error Tolerant Error Detecting Latch for Sub/Near-Threshold Applications," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 366-375, June 2020
J10. Priyamvada Sharma, Poorvi Jain and Bishnu Prasad Das, "An Optimal Device Sizing for a Performance-Driven and Area-Efficient Subthreshold Cell Library for IoT Applications" in Elsevier Microelectronics Journal, Volume 92, 2019, 104613.
J9. Poorvi Jain and Bishnu Prasad Das, "Reducing the Impact of Local Load Variation on the DUT in a Process Detector Using a Supply Controlled Ring Oscillator," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 4, pp. 605-612, Nov. 2019
J8. Poorvi Jain and Bishnu Prasad Das, "On-Chip Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator," in IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 2, pp. 226-235, May 2019.
J7. Govinda Sannena and Bishnu Prasad Das, "Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 7, pp. 1223-1232, July 2018.
J6. Govinda Sannena and Bishnu Prasad Das, "Metastability immune and area efficient error masking flip-flop for timing error resilient designs", in Elsevier Integration, the VLSI Journal Vol. 61, Pages 101-113, March 2018
J5. Bishnu Prasad Das and Hidetoshi Onodera, “Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs,” in IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 12, pp. 2535-2548, Dec. 2014.
J4. Bishnu Prasad Das and Hidetoshi Onodera, “On-chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator,” IEEE Transactions on Circuits and Systems II, Vol. 61, No. 3, Mar 2014, pp. 183-187.
J3. Bishnu Prasad Das and Hidetoshi Onodera, “Area-Efficient Reconfigurable-Array-Based Oscillator for Standard Cell Characterization,” IET Circuits Devices Syst., Vol. 6, Iss. 6, pp. 429–436, Nov. 2012.
J2. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, “Voltage and Temperature Aware SSTA Using Neural Network Delay Model,” IEEE Transactions on Semiconductor Manufacturing, vol. 24, No. 4, pp. 533- 544, Nov. 2011.
J1. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, “Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator,” IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No. 2, pp. 256-267, May 2009.
C17. Poorvi Jain and Bishnu Prasad Das, "On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch", Accepted in ICMTS conference 2019 at Kita-kyushu City, Japan
C16. Swaati and Bishnu Prasad Das, " A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-low Power Applications", 21st International Symposium on VLSI Design and Test (VDAT), 2017, Roorkee, India.
C15. Poorvi Jain and Bishnu Prasad Das, "Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring Oscillator", IEEE VLSI Design conference, 2017, Hyderabad, India.
C14. Govinda Sannena and Bishnu Prasad Das, "Area and Power-efficient Timing Error Predictor for Dynamic Voltage and Frequency Scaling Application," IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), December 19-21, 2016, Gwalior, India
C13. Govinda Sannena and Bishnu Prasad Das, "A Metastability Immune Timing Error Masking FlipFlop for Dynamic Variation Tolerance," ACM GLSVLSI, Boston, USA, May, 2016.
C12. Kaushik Vaidyanathan, Bishnu P Das and Larry Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack,” IEEE/ACM Design Automation Conference (DAC), June, 2014
C11. Kaushik Vaidyanathan, Bishnu P Das, Ekin Sumbul, Renzhi Liu, Larry Pileggi, “Building trusted ICs using split fabrication,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2014
C10. Bishnu Prasad Das and Hidetoshi Onodera, “Reconfigurable Array-Based Area-Efficient Test Structure for Standard Cell Characterization,” IEEE Twelfth Workshop on RTL and High Level Testing, 2011.
C9. Bishnu Prasad Das and Hidetoshi Onodera, “Warning Prediction Sequential for Transient Error Prevention,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2010.
C8. Bishnu Prasad Das and Hidetoshi Onodera, “Accurate Individual Gate Delay Measurement to Study Within-die Variations”, IEICE Spring meeting, Sendai, Japan, March 2010
C7. Bishnu Prasad Das, “Delay Variability: Modeling and On-chip Measurement”, PhD Forum, Design Automation & Test in Europe, Nice, France, April, 2009
C6. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, N.V.Arvind, V. Visvanathan, “Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator”, IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, September 2008.
C5. Bishnu Prasad Das, Janakiraman V, B Amrutur, H.S. Jamadagni, N.V. Arvind, “Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations”, IEEE VLSI Design Conference, Hyderabad, India, Jan 2008
C4. Janakiraman V, Bishnu Prasad Das, B Amrutur, “Voltage and temperature scalable standard cell leakage models based on stacks for statistical leakage characterization”, IEEE VLSI Design Conference, Hyderabad, India, Jan 2008.
C3. Bishnu Prasad Das, Bharadwaj Amrutur, H S Jamadagni “Voltage scalable statistical gate delay models using neural networks”, 11th IEEE VLSI Design And Test Symposium, Kolkota, India, 2007.
C2. Janakiraman, Bishnu Prasad Das, Vish Visvanathan and B. Amrutur, "Leakage modeling of logic gates considering effect of input vectors", 11th IEEE VLSI Design And Test Symposium, Kolkota, India, 2007
C1. Bishnu Prasad Das, Bharadwaj Amrutur, H.S.Jamadagni, “Critical Path Modeling for Dynamic Voltage Scaling (DVS) in Low Power Applications”, 10th IEEE VLSI Design and Test Symposium, Goa, India, 2006.