IIT Roorkee Homepage
  • Gowrish B
  • Darshak Bhatt
  • Tharun Kumar Reddy Bollu
  • Anand Bulusu
  • Ashish Kumar Chowdhary
  • Bishnu Prasad Das
  • Avirup Dasgupta
  • Sudeb Dasgupta
  • Arnab Datta
  • Utpal Dey
  • Devesh Dwivedi
  • Debashis Ghosh
  • Anshul Jaiswal
  • MV Kartikeyan
  • Priyansha Kaurav
  • Brajesh Kumar Kaushik
  • Saurabh Khanna
  • Brijesh Kumar
  • Dheeraj Kumar
  • Saravana Kumar M
  • Sanjeev Manhas
  • Sparsh Mittal
  • Akhilesh Mohan
  • Rajib Kumar Panigrahi
  • Vinod Pankajakshan
  • Nagendra P. Pathak
  • Amalendu Patnaik
  • Vishvendra Singh Poonia
  • Pyari Mohan Pradhan
  • Tanmoy Pramanik
  • Karun Rawat
  • Meenakshi Rawat
  • Sourajeet Roy
  • Abhay Kumar Sah
  • Biplab Sarkar
  • Ekant Sharma
  • Dharmendra Singh
  • Sandeep Kumar Singh
  • Anshul Tyagi
anand.bulusu@ece.iitr.ac.in

Anand Bulusu

ECE DEPARTMENT

Professor

From To Designation Organisation
2006 2007 Sr. Research Engineer IIT Bombay
2007 2008 Sr. Design Engineeer Freescale Semiconductor India (Presently NXP Semiconductrs)
2008 2014 Assistant Professor IIT Roorkee
2014 Present Associate Professor IIT Roorkee
Degree Subject University Year
Ph.D Microelectronics IIT Bombay 2006
From To Designation Organisation Level
2013 On going Faculty Advisor IEEE CAS Student Chapter, IIT Roorkee
2014 On going Branch Counsellor IEEE Student Branch
Topic Funding Agency Year
Robust Methodology for Nanoscale VLSI Circuit Design Considering Layout Dependent Variatiations DST 2013
A robust and scalable VLSI test methodology for high performance CMOS designs considering spatial an Semiconductor Research Corporation 2018
Development and Efficient Characterization of FB and DT CMOS PDSOI Standard Cell Libraries DST (AMT) 2019
Nanoscale FinFET Device and Circuit Design Methodology DST 2009
Negative capacitance fet (NCFET): fabrication/modeling/simulation for design of digital circuits DST Nano Mission 2019
An Energy Efficient IOT Processor using an Optimized Near-Threshold Voltage Standard Cell Library IMPRINT-2 (SERB) 2019
Chips to Systems Design (SMDP) DIETY 2015
ICT Academy DIETY 2016
  • IEEE Circuits and Systems Society, Member
  • IEEE Electron Device Society, Member
  • IEEE Solid State Circuits Society, Member
Title Course Code Class Name Semester
Fundamentals of Microelectronics EC 344 UG Spring
Analog Circuits EC 205 UG Autumn
Digital VLSI Circuit Design EC 573 PG + UG Spring
Semiconductor Devices EC 142 U.G. Spring
Analog VLSI Circuit Design EC 581 PG Spring
Automatic Control Systems EC 222 UG Spring
Electronic Network Theory EC 291 UG Autumn
Fundamentals of Electronics EC 102 U.G. Spring
Topic Scholar Name Status of PHD Registration Year
FinFET Device-Circuit interaction (Analog Domain) Shashank Bancchor O 2015
NC-TunnelFET Devie-Circuit Interaction Khoiram Johnson O 2019
NCFET Device-Circuit Interaction Amit Bahera O 2019
Variation Aware Timing Models of CMOS Circuits Lomash Acharya O 2019
Near Threshold Standard Cell Design and Characterization Mahipal D. O 2019
Circuit design for in-memory computing Dinesh Kushwaha O 2018
Tunnel FET Device-Circuit Interaction Abhishek Acharya A 2015
CMOS PLL Design Neeraj Mishra O 2016
Low Voltage CMOS VCO Design Lalit Dani O 2015
Near Threshold CMOS Digital Circuit Design and Analysis Inder Chaudhary O 2014
FinFET device-circuit interaction in low-voltage domain Sarita Yadav O 2016
Mechanical Stress Aware Nanoscale VLSI Circuit Design Methodologies Arvind Sharma A 2013
Radiation hard data converters Ashutosh Yadav O 2019
Modeling of FinFET device parasitics Archana Pandey A 2012
TunnelFET device-circuit co-design Menaka A 2010
Device-circuit co-design of Silicon Nanowire transistor Satish Maheshwaram A 2010
Performance models for nanoscale VLSI circuits Baljit Kaur A 2010
Robust circuit design methodology for nanoscale VLSI technologies Naushad Alam A 2009
Couse Name Sponsored By Date
Design Issues in Nanoscale VLSI Circuits and Systems QIP June 2010
Title Place Date
FinFET Logic Gate Capacitances: Impact of Circuit Level Parameters IEEE Indicon 2013, IIT Bombay 14.12.13
FinFET Device Circuit Co-Design: Issues and Challenges IEEE VLSI Design Conference 2015, Bangalore 04.01.2015
Nanoscale VLSI Circuit Design: Timing Issues and Solutions NITTTR, Chandigarh 09.10.2016
Topic Organisation Level
Process variation aware Standard Cell extraction Freescale Semiconductor India Pvt. Ltd. PG
Tunnel FET Device Modeling ST Microelectronics PG
CMOS VCO Design ST Microelectronics PG
High Speed Circuits Global Foundries PG
SRAM Yield Analysis ARM NOIDA PHD

 

  • I give letters of recommendation to only the following: 1. My BTP or M.Tech dissertation students. 2. Students who did a project with me: Only PhD or MS leading to PhD applications. 3. Students who secured at least a 9 (B+) in my course(s): Only PhD or MS leading to PhD applications.