Bishnu Prasad Das – ECE Department | IIT Roorkee

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Bishnu Prasad Das

Professor

Email : bishnu.das[at]ece.iitr.ac.in
Phone: 01332-284798
Room No. : S 125
My Website

In-memory computation
RISC-V Processor Architecture
VLSI Architecture for DSP algorithm
Crypto-processor and Hardware security
Ultra-Low power circuit design
Phase Locked Loop
Wearable healthcare devices

From	To	Designation	Organisation
2012	2013	Post Doctoral Researcher	CMU, Pittsburgh, USA
2009	2012	Post Doctoral Researcher	Kyoto University, Japan

Degree	Subject	University	Year Studied
Ph.D.	Electronics Design & Technology	IISc, Bangalore	2009

Award	Institute	Year Awarded
Faculty Fellow	DivyaSampark iHUB Roorkee	2022-23
Best Tapeout Award	VLSI design conference	2025
Young Faculty Research Fellowship (YFRF)	Ministry of Electronics & Information Technology (MeitY), Government of India	2018

Scheme	Sponsoring Agency	Other Faculties	Year Sponsored
Design and on-chip characterization of standard cell library	FIG		2015
Design of Voltage-Scalable and Process Variation Tolerant Standard Cell Library	SERB		2016
SMDP C2SD (Chips to Systems Design)	MEITY		2015

IEEE Senior Member

Title	Course Code	Course	Semester
Analog VLSI Circuit Design	ECN-581	M.Tech., B.Tech IV, Ph.D	Autumn
VLSI Physical Design	ECN-591	M.Tech., B.Tech IV, Ph.D	Spring
Digital System Design	ECN-578	M.Tech., B.Tech IV, Ph.D	Autumn
IC Application Laboratory	ECN-351	B.Tech III	Autumn
Digital Electronic Circuits Laboratory	ECN-252	B.Tech II	Spring
Microelectronic Devices,Technology and Circuits	ECN-341	B.Tech III	Autumn
Training and Seminar	EC-491	B.Tech IV	Autumn
DIGITAL LOGIC DESIGN	ECN-104	BTech (CSE)	Spring
Digital Logic Design	ECN-104	BTech (CSE)	Spring

Topic	Scholar Name	Status of PhD	Registration Year
Resilient Circuit Design	Sannena Govinda	A	2014
Sub-threshold Standard Cell Design	Priyamvada Sharma	A	2014
On-chip Process Variation Measurement	Poorvi Jain	A	2015
Memory Design	Prasanna Kumar Saragada	O	2017
DSP architectures	Anu Verma	O	2018
Soil Sensors	Aranya Gupta	O	2020
Memory Design	Amandeep Singh	O	2020
Ultra-low power circuit design	Anant Kumar Singh	O	2021
PLL Design	Anshul Verma	O	2019
Hardware security	Vishal Pal	O	2024
RISC-V Processor	Nithin Krishna, M.S.	O	2024
In-memory Computation (IMC)	Samiksha Singh Chauhan	O	2024
DSP Architecture	Abhishek Verma	O	2024
Hardware Security	Kunal Kranti Das	O	2022

P1. Bharadwaj Amrutur and Bishnu Prasad Das, “Gate Delay Measurement Circuit and Method of Determining a Delay of a Logic Gate” US patent No. 8,224,604 B1 and date of Patent July 17, 2012.
P2. Lawrence Pileggi, Bishnu P. Das, Kaushik Vaidyanathan, “Testing integrated circuits during split fabrication,” Application No: PCT/US2015/012220, Publication no: WO2015160405 A3, Publication date, Dec 10, 2015.