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Anand Bulusu

Professor

Email : anand.bulusu@ece.iitr.ac.in
Phone: 01332-285347
Room No. : N113
My Website Link

  • CMOS Digital Circuits,
  • VLSI Devices,
  • Mixed-Signal Design,
  • Low Voltage CMOS Circuit Design and Modeling
From To Designation Organisation
2006 2007 Sr. Research Engineer IIT Bombay
2007 2008 Sr. Design Engineeer Freescale Semiconductor India (Presently NXP Semiconductrs)
2008 2014 Assistant Professor IIT Roorkee
2014 2019 Associate Professor IIT Roorkee
2019 Present Professor IIT Roorkee
Degree Subject University Year Studied
Ph.D Microelectronics IIT Bombay 2006
FromToDesignationOrganizationLevel
2013On goingFaculty AdvisorIEEE CAS Student Chapter, IIT Roorkee 
2014On goingBranch CounsellorIEEE Student Branch 
2021OngoingChairmanM.Tech (VLSI) for Working Industry Professionals, IIT Roorkee–
  • Member IEEE Circuits and Systems Society
  • Member IEEE Electron Device Society
  • Member IEEE Solid State Circuits Society
TitleCourse CodeCourseSemester
Fundamentals of MicroelectronicsEC 344UGSpring
Analog CircuitsEC 205UGAutumn
Digital VLSI Circuit DesignEC 573PG + UGSpring
Semiconductor DevicesEC 142U.G.Spring
Analog VLSI Circuit DesignEC 581PGSpring
Automatic Control SystemsEC 222UGSpring
Electronic Network TheoryEC 291UGAutumn
Fundamentals of ElectronicsEC 102U.G.Spring
TopicScholar NameStatus of PhDRegistration Year
FinFET Device-Circuit interaction (Analog Domain)Shashank BancchorA2015
NC-TunnelFET Devie-Circuit InteractionKhoiram JohnsonO2019
Circuit design for in-memory computingDinesh KushwahaO2018
Tunnel FET Device-Circuit InteractionAbhishek AcharyaA2015
CMOS PLL DesignNeeraj MishraA2016
Low Voltage CMOS VCO DesignLalit DaniA2015
Near Threshold CMOS Digital Circuit Design and AnalysisInder ChaudharyA2014
FinFET device-circuit interaction in low-voltage domainSarita YadavA2016
Mechanical Stress Aware Nanoscale VLSI Circuit Design MethodologiesArvind SharmaA2013
Modeling of FinFET device parasiticsArchana PandeyA2012
TunnelFET device-circuit co-designMenakaA2010
Device-circuit co-design of Silicon Nanowire transistorSatish MaheshwaramA2010
Performance models for nanoscale VLSI circuitsBaljit KaurA2010
Robust circuit design methodology for nanoscale VLSI technologiesNaushad AlamA2009
Analog Circuit Design in PDSOI TechnologiesHS JattanaO2019
Radiation Hard Circuit Design at Cryogenic TemperatureAshutosh YadavO2019
NCFET Device Circuit InteractionAmit BaheraO2019
Near Threshold Standard Cell DesignMahipal D.O2019
Variation Aware Efficient Standard Cell CharacterizationLomash AcharyaO2019
Design Methodology for Compute-in- Memory SRAM MacroNeha GuptaO2020
Energy Harvesting System and Power Management CircuitsKartikay Mani TripathiO2020
Mixed Signal DesignRaviO2021
NCFET Device-Circuit InteractionNitanshu ChauhanA2017
In Memory Computation Using Emerging Non Volatile Memories.Abhishek GoelO2022
RF Device Circuit InteractionsNarendra Pratap SinghO2022
CMOS OscillatorShubham SharmaO2023
TitlePlaceDate Delivered
FinFET Device Circuit Co-Design: Issues and ChallengesIEEE VLSI Design Conference 2015, Bangalore04.01.2015
Nanoscale VLSI Circuit Design: Timing Issues and SolutionsNITTTR, Chandigarh09.10.2016
TopicOrganisationLevel
Process variation aware Standard Cell extractionFreescale Semiconductor India Pvt. Ltd.PG
Tunnel FET Device ModelingST MicroelectronicsPG
CMOS VCO DesignST MicroelectronicsPG
High Speed CircuitsGlobal FoundriesPG
SRAM Yield AnalysisARM NOIDAPHD

Selected Publications in International Journals: 

  • Mahipal Dargupally, Lomash Chandra Acharya, Arvind Kumar Sharma, Sudeb Dasgupta and Anand Bulusu “A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime.” IEEE Transactions on Very Large-Scale Integration Systems 2024 (Accepted: DOI: 10.1109/TVLSI.2024.3504856)
  • A. Kumar, S. Mehrotra, A. Bulusu and A. Dasgupta, “Performance Projection of Gate-All-Around (GAA)-Based Negative Capacitance Complementary FET (NC-CFET) Relative to Standard CFET,” in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2024.3503283.
  • Abhishek Kumar, N. Mishra, A. Bulusu, S. Mehrotra and A. Dasgupta, “Impact of Doped Hafnium Oxides on Memory Window and Low-Frequency Noise in Ferroelectric FETs,” in IEEE Transactions on Electron Devices, vol. 71, no. 7, pp. 4015-4020, July 2024, doi: 10.1109/TED.2024.3400126
  • Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta, Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs, Solid-State Electronics,Volume 216,2024,108932,ISSN 0038-1101
  • Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations,Microelectronics Journal,Volume 142,2023,105981,
  • Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu “Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network,” in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2023.3329261.
  • Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta, Exploring the Impact of Domain Numbers on Negative Capacitance Effects in Ferroelectric Device-Circuit Co-Design, Solid-State Electronics,2023,108792, ISSN 0038-1101,https://doi.org/10.1016/j.sse.2023.108792.
  • Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Mahipal Dargupally, Neeraj Mishra, Arvind Kumar Sharma, Abhishek Acharya, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu, Prediction of Variation Aware Fosc in Ring Oscillators (ROs) to Mitigate Aging Impact on RO-PUF, Solid-State Electronics,2023,108790, ISSN 0038-1101,https://doi.org/10.1016/j.sse.2023.108790.
  • Abhishek Kumar, M Ehteshamuddin, Amol D Gaidhane, Anand Bulusu, Shruti Mehrotra, Avirup Dasgupta “Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors,” in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2023.3287825.
  • Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Sudipto Chakraborty, Anand Bulusu.”Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs,” in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2023.3267384.(2023)
  • Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu “Aging Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2022.3231173.
  • Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv Joshi, Sudeb Dasgupta, Anand Bulusu et al., “Phase Noise Analysis of Separately Driven Ring Oscillators,” in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi: 10.1109/TCSI.2022.3196820. 
  • Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta. Understanding negative capacitance physical mechanism in organic ferroelectric capacitor Solid-State Electronics Vol 194 Pages 108350 August 2022.
  • Sarita Yadav, Nitanshu Chauhan, Raghav Chawla, Arvind Sharma, Shashank Banchhor, Rajendra Pratap Bulusu Anand. Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs Vol 37 Pages085023 July 2022.
  • J. Singh, N. Chauhan, A. Bulusu and S. Dasgupta, “Physical Cause and Impact of Negative Capacitance Effect in Ferroelectric P(VDF-TrFE) Gate Stack and Its Application to Landau Transistor,” in IEEE OpenJournal of Ultrasonics, Ferroelectrics, and Frequency Control, vol. 2, pp. 55-64, 2022, doi: 10.1109/OJUFFC.2022.3172665.
  • Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V Joshi, Sudeb Dasgupta, Anand Bulusu ., “An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2311-2315, April 2022,doi: 10.1109/TCSII.2022.3149818.
  • Nitanshu Chauhan, Navjeet Bagga, Shashank Banchhor, Chirag Garg, Arvind Sharma, Arnab Datta, S Dasgupta, Anand Bulusu.BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective Nanotechnology Vol 33 Page 085203 December 2021.
  • Sarita Yadav, Nitanshu Chauhan, Shobhit Tyagi, Arvind Sharma, Shashank Banchhor, Rajiv Josh Rajendra Pratap, Anand Bulusu.Physical insight into variation aware minimum V DD for the deep subthreshold operation of FinFET.Semiconductor Science and Technology Vol 36 Pages 125002 October 2021.
  • Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta and A. Bulusu, “Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits,” in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 69, no. 1, pp.430-437, Jan. 2022, doi: 10.1109/TUFFC.2021.3116897.
  • Chirag Garg, Nitanshu Chauhan, Arvind Sharma, Shashank Banchhor, Aditya Doneria, Sudeb Dasgupta, Anand Bulusu. “Investigation of Trap-Induced Performance Degradation and Restriction on HigherFerroelectric Thickness in Negative Capacitance FDSOI FET,” in IEEE Transactions on Electron Devices,vol. 68, no. 10, pp. 5298-5304, Oct. 2021, doi: 10.1109/TED.2021.3105952.
  • Lalit Mohan Dani, Neeraj Mishra, and Anand Bulusu,” A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime” Accepted for publication in IEEE Transactions on Circuits and Systems II: Express Briefs.
  • Khoirom Johnson Singh, Sudeb Dasgupta and Anand Bulusu, “Origin of Negative Capacitance Transient in Ultrascaled Multidomain Metal-Ferroelectric-Metal Stack and Hysteresis-Free Landau Transistor” Accepted for publication in IEEE Transactions on Electron Devices.
  • Nitanshu Chauhan, Navjeet Bagga, Shashank Banchhor, Arnab Dutta, Sudeb Dasgupta and Anand Bulusu, “Negative to Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits” Accepted for publication in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control.
  • Garg, N.Chauhan, A.Sharma, S.Banchhor, A.Doneria, S.Dasgupta and Bulusu Anand,”Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET,” Accepted for publication in IEEE Transactions on Electron Devices.
  • Banchhor, N. Chauhan and Bulusu Anand, “A new physical insight into the zero temperature coefficient with self-heating in silicon-on-insulator FinFET, ” Accepted for publication in Journal of IOP Science Semicond. Sci. Technol. 2021, vol. 36, no. 3, 035005. doi: 10.1088/1361-6641/abd220
  • Neeraj Mishra, Lalit M Dani, S Chakraborty, R V Joshi and Bulusu Anand, “Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Usings ROs,” Accepted for publication in IEEE Transactions on Circuits and Systems II: Express Briefs.
  • Lalit M Dani, Neeraj Mishra and Bulusu Anand, “An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor based VCO Architectures,” Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
  • Neeraj Mishra, Lalit M Dani, Kunal Sanvaniya, S. Dasgupta, S.Chakraborty and Anand Bulusu, “Design and Realization of High-Speed Low-Noise Multi-loop Skew-based ROs Optimized for Even/Odd Multi-Phase Signals,” Accepted for publication in IEEE Transactons on Circuits and Systems II: Express Briefs.
  • Chaudhry I. Kumar and Bulusu Anand, “A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design, Accepted for pubilcation in IEEE Transactions on Device and Material Reliability.
  • Lalit Dani, N. Mishra, A. Sharma, Bulusu Anand, “Variation Aware Prediction of Circuit Performance in Near-threshold Regime using Supply Independent Transition Threshold Points,” Accepted for publication in IEEE Transactions on Electron Devices.
  • Kumar and B. Anand, “A Highly Reliable and Energy Efficient Triple-Node-Upset Tolerant Latch Design”, Accepted for publication in IEEE Transactions on Nuclear Science.
  • Abhishek Acharya, A. B. Solanki, S. Glass, Q. T. Zhao, and Bulusu Anand, “Impact of Gate-Source Overlap on the Device/ Circuit Analog Performance of Line TFETs,” Accepted for publication in IEEE TED.
  • Shashank Banchhor, Kintada Dinesh Kumar, Ashish Dwivedi and Bulusu Anand, “A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits,” Accepted for publication in IEEE TED.
  • Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal,H.S. Jatana, and Anand Bulusu, “A Physics based Variability Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches,” Accepted for publication in IEEE Transactions on VLSI.
  • Chaudhry Indra Kumar and Bulusu Anand, “High Performance Energy Efficient Radiation Hardened Latch for Low Voltage Applications,” Elsevier VLSI Journal of Integration, Accepted for publication.
  • Chaudhry Indra Kumar, Arvind K. Sharma, Rajendra Partap, Anand Bulusu, “An energy-efficient variation aware self-correcting latch,” Elsevier Microelectronics Journal, pp. 67 – 78, February 2019.
  • Chaudhry Indra Kumar and Bulusu Anand, “Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell,” IET Electronics Letters, pp. 1423 – 1424, December 2018.
  • Arvind Sharma, Naushad Alam and Anand Bulusu, “Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design Techniques,” IEEE Transactions on Electron Devices, pp. 2413 – 2421, June 2018.
  • Abhishek Acharya, Abhishek Solanki, Sudeb Dasgupta and Bulusu Anand, “Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective,” IEEE Transactions on Electron Devices, Volume: 65, Issue: 1, Jan. 2018.
  • Om Prakash , Satish Maheshwaram,Mohit Sharma Anand Bulusu , Sanjeev K. Manhas, “Performance and Variability Analysis of SiNW 6T-SRAM Cell using Compact Model with Parasitics,” IEEE Transactions on Nanotechnology , Volume: 16, Issue: 6, Nov. 2017.
  • Om Prakash, Swen Beniwal, Satish Maheshwaram, Anand Bulusu, Navab Singh, and S. K. Manhas, “Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 2, JUNE 2017.
  • Arvind Sharma, Naushad Alam and Anand Bulusu, “Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design,” IEEE Transactions on Electron Devices, 2017.
  • Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “A Novel VDSAT Extraction Method for Tunnel FETs and Its Implication on Analog Design,” IEEE Transactions on Electron Devices, pp. 629-623, February 2017.
  • Arvind Sharma, Naushad Alam, Sudeb Dasgupta, Bulusu Anand, “Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits”, IEEE Transactions on Electron Devices, PP, no. 99, 2016. 
  • Baljit Kaur, Arvind Sharma, Naushad Alam, Sanjeev K. Manhas, Bulusu Anand, “A Variation Aware Timing Model for a 2-Input NAND Gate and Its Use in Sub-65nm CMOS Standard Cell Characterization”, Microelectronics Journal (Elsevier), vol. 53, pp. 45-55, 2016.
  • Archana Pandey; Harsh Kumar; S. K. Manhas; Sudeb Dasgupta; Bulusu Anand , “Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and significance” , IEEE Transactions on Electron Devices, pp. 1392-1396, march 2016.
  • Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand, “Efficient ECSM characterization considering voltage, temperature and mechanical stress variability,” Accepted for publication in IEEE Transactions on Circuits and Systems – I, October 2014.
  • Gaurav Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Novel Design Methodology Using Lext Sizing in Nanowire CMOS Logic” IEEE Transactions on Nanotechnology, pp. 650-658, July 2014.
  • Naushad Alam, Bulusu Anand and Sudeb Dasgupta, “An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design,” IEEE Transactions on Circuits and Systems -I, pp. 1714-1726, June 2014.
  • Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta,  Bulusu Anand, “Effect of Load Capacitance and Input Transition Time on Underlap FinFET Capacitance,” IEEE Transactions on Electron Devices, pp. 30-36, January 2014.
  • Ashwani Kumar, Vishvendra Kumar, Bulusu Anand, S. Manhas, “Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance,” IEEE Transactions on Nanotechnology, pp. 16-22, January 2014.
  • Menka, Bulusu Anand and Dasgupta S., “Two Dimensional Analytical Modeling for Asymmetric 3T and 4T Double Gate Tunnel FET in Subthreshold Region: Potential and Electric Field”, Elsevier Microelectronics Journal, pp. 1251-1259, December 2013.
  • Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, “Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis,” IEEE Transactions on Electron Devices, vol. 60, no. 9, pp. 2943-2950, September 2013.
  • Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Variable Taper CMOS Buffer Design”, Elsevier Microelectronics Reliability, vol. 53, Issue 5, pp. 718-724, May 2013.
  • Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress on CMOS Buffer Design using Multi-Fingered Devices”, Elsevier Microelectronics Reliability, vol. 53, Issue 3, pp. 379-385, March 2013.
  • Alam, B. Anand, and S. Dasgupta, “Gate-Pitch Optimization for Circuit Design using Strain-Engineered Multi-Finger Gate Structures”, IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3120-3123, November 2012.
  • Gaurav Kaushal, S. Manhas, S. Maheshwaram, S. Dasgupta, A. Bulusu and N. Singh, “Tuning source/drain extension profile in current matching in nanowire CMOS logic,” IEEE Transactions in Nanotechnology, vol. 11, no. 5, pp. 1033-1035, September 2012.
  • Satish Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, “Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform,”  IEEE Electron Device Letters, vol.33, no. 7, pp.934-936, July 2012.
  • Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab Singh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS,” IEEE Electron Device Letters, pp. 1011-1013, August 2011.
  • Pradeep Kumar Chawda, B. Anand, V. Ramgopal Rao, “Optimum Body Bias constraints for leakage reduction in high-K Complementary Metal Oxide Semiconductor Circuits,” Japanese Journal of Applied Physics (JJAP), May 2009.
  • Bulusu Anand, M. P. Desai, and V. Ramgopal Rao, “Silicon Film Thickness Optimization for SOI-DTMOS from Circuit Performance considerations”, IEEE Electron Device Letters, pp. 436-438, June 2004.
  • Sivaram, B. Anand, M. P. Desai, “Silicon film thickness considerations for SOI-DTMOS,” IEEE Electron Device Letters, pp. 276-278, May 2002.

Selected Publications in International Conferences:

  • Nitanshu Chauhan, Amit Kumar Behera, Chirag Garg, Sudeb Dasgupta, Anand Bulusu “Impact of Non-Uniform Ferroelectric Dielectric Phase and Metal Grains on the Performance of MFM Capacitor and Ferroelectric FETs,” 2023 IEEE International Symposium on Applications of Ferroelectrics (ISAF), Cleveland, OH, USA, 2023, pp. 1-4, doi: 10.1109/ISAF53668.2023.10265412.
  • Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu”Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure,” 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Funchal, Portugal, 2023, pp. 1-4, doi: 10.1109/SMACD58065.2023.10192158.
  • Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V Joshi, S Dasgupta, Anand Bulusu”A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application,” 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5, doi: 10.1109/AICAS57966.2023.10168599.
  • Shashank Banchhor, Navjeet Bagga, Nitanshu Chauhan, S Manikandan, Avirup Dasgupta, S Dasgupta, Anand Bulusu”A New Insight into the Saturation Phenomenon in Nanosheet Transistor: A Device Optimization Perspective,” 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, doi: 10.1109/EDTM55494.2023.10102974.
  • Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep miryala, Rajiv Joshi, Sudeb Dasgupta, and Anand Bulusu “An Energy -Efficient Multi-bit current-based Analog Compute in Memory Architecture and Design Methodology,” VLSI Design Conference, January 2023, Hyderabad.
  • Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta, “Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm,” VLSI Design Conference, January 2023, Hyderabad.
  • Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta et al., “Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications,” 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 292-296, doi:10.1109/VLSID2022.2022.00063.
  • Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra and A. Dasgupta,”Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs,” 2022 IEEE International Conference on emerging Electronics (ICEE), Bangalore, India, 2022,pp. 1-5, doi: 10.1109/ICEE5620310118175.
  • Subramaniyan, N. Chauhan, N. Bagga, A. Kumar, S. K. Banchhor, S. Roy, A. Dasgupta, A. Bulusu and S. Dasgupta, “Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors,” 2022 IEEE International Conferenceon Emerging Electronics (ICEE), Bangalore, India, 2022, pp1-4, doi: 10.1109/ICEE56203.2022.10117608.
  • Prakash, A. Yadav, A. Bulusu and S. Dasgupta, “A Novel High RSNM RHBD 16T SRAM Cell at 180nm,” 2021 IEEE 18th India Council International Conference (INDICON), 2021, pp. 1-5, doi: 10.1109/INDICON52576.2021.9691597.
  • Yadav, A. Bulusu, S. Dasgupta and S. Singh, “Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm,” 2021 International Conference on Microelectronics (ICM), 2021, pp. 166-169, doi: 10.1109/ICM52667.2021.9664963.
  • Yadav, N. Chauhan, A. Pandey, R. Pratap and A. Bulusu, “Behaviour of FinFET Inverter’s Effective Capacitances in Low-Voltage Domain,” 2021 25th International Symposium on VLSI Design and Test (VDAT), 2021, pp. 1-5, doi: 10.1109/VDAT53777.2021.9601052.
  • Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv Joshi, Sudeb Dasgupta, Anand Bulusu.”A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 1556-1560, doi: 10.1109/ISCAS48785.2022.9937908.2022
  • J. Singh, A. Bulusu and S. Dasgupta, “Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401100.
  • J. Singh, A. Bulusu and S. Dasgupta, “Ultrascaled Multidomain P(VDF-TrFE) Organic Ferroelectric Gate Stack to the Rescue,” 2021 IEEE Latin America Electron Devices Conference (LAEDC), 2021, pp. 1-4, doi: 10.1109/LAEDC51812.2021.9437926.
  • Banchhor, N. Chauhan, A. Doneria and B. Anand, “Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect,” 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, pp. 199-203, doi:10.1109/VLSID51830.2021.00039.
  • Bagga, N. Chauhan, A. Bulusu and S. Dasgupta, “Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET,” 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), 2019, pp. 102-105, doi: 10.1109/MOS-AK.2019.8902381.
  • Chauhan et al., “Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases onMultidomain MFIM Capacitor and Negative Capacitance FDSOI,” 2022 IEEE International Reliability Physics Symposium (IRPS), 2022, pp. P23-1-P23-6, doi: 10.1109/IRPS48227.2022.9764552.
  • C. Acharya, A. k. Sharma, V. Ramakrishan, A. Mandal, S. Dasgupta and A. Bulusu, “Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization,” 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 251-256, doi:10.1109/ISQED51717.2021.9424341.
  • Lalit M. Dani, Neeraj Mishra and Anand Bulusu, “MOS Varactor RO architectures in Near Threshold Regime using Forward Body Biasing techniques,” VLSI Design Conference, January 2019, Delhi.
  • Lalit M. Dani, N. Mishra, S.K. Banchhor, S. Miryala, A. Doneria, Bulusu Anand, “Design and Characterization of Bulk Driven MOS Varactor Based VCO at Near Threshold Regime,” IEEE-S3S, San Francisco, October 2018.
  • Chawla, S. Yadav, A. Sharma, B. Kaur, R. Pratap and Bulusu Anand, “TSV Induced Stress Model and Its Application in Delay Estimation,” IEEE-S3S, San Francisco, October 2018.
  • Arvind Sharma, Naushad Alam, Raghav Chawla,Bulusu Anand, “Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure,” International Symposium on Devices, Circuits and Systems (ISDCS), Howrah.
  • Inder Kumar and Bulusu Anand “Design and Analysis of Energy-Efficient Self-Correcting Latches Considering Metastability,” IEEE PRIME, July 2018, Prague.
  • Sharma, N. Alam, A. Bulusu, “UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective,” IEEE PRIME, July 2018, Prague.
  • Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu, “A Modified Method of Logical Effort for FinFET Circuits considering of Fin-Extension Efforts,” Proceedings of IEEE ISQED-2018, Santa Clara.
  • Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, “Impact of Device Design Parameters on VDSAT and Analog Performance of TFETs,” Presented at IEEE Silicon Nanoelectronics Workshop 2017, Japan.
  • Chaudhry Indra Kumar, A. Sharma, S. Miryala, Bulusu Anand, “A novel energy-efficient self-correcting methodology employing INWE,” IEEE SMACD, 2016, Lisbon.
  • Sayyaparaju Sagar Varma, A. Sharma, Bulusu Anand, “An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis,” IEEE SMACD, 2016, Lisbon.
  • Archana Pandey, Harsh Kumar, Praanshu Goyal, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand “FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay” , IEEE VLSI Design, 2016, Kolkata.
  • Arvind Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, and Bulusu Anand, “Pre-layout Estimation of Performance and Design of Basic Analog Circuits in Stress Enabled Technologies” in IEEE VDAT, 2015.
  • Yogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, and Bulusu Anand, “Timing Model for Two Stage Buffer and Its Application in ECSM Characterization”, in IEEE VDAT, 2015.
  • Sharma, Y. Sharma, S. Dasgupta, and B. Anand, “Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model”, IEEE ISQED-2015.
  • Parmanand Singh,V. Asthana, R. Sithanandam, A. Bulusu, S. Dasgupta, “Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor,” IEEE VLSI Design, 2014.
  • Bijay Kumar Dalai, A. Bulusu, N. Kannan and Arvind Kumar Sharma, “An Empirical Delta Delay Model for Highly Scaled CMOS Inverter Considering Well Proximity Effect,” VDAT 2014.
  • Arvind Kumar Sharma, Naushad Alam, Sudeb Dasgupta and Bulusu Anand, “The Impact of Process-Induced Mechanical Stress on D-Latch Timing Performance,” Accepted in IEEE IMPACT 2013.
  • Saurabh K. Nema, M. SaiKiran, P. Singh, Archana Pandey, S. K. Manhas, A. K. Saxena, Anand Bulusu, “Improved Underlap FinFET with Asymmetric Spacer Permittivities,” Accepted in IWPSD 2013.
  • Maheshwaram, S.K. Manhas, G. Kaushal, and B. Anand, “Vertical Nanowire MOSFET Parasitic Resistance Modeling,” in Proc. IEEE EDSSC 2013, Hong Kong.
  • Prahlad Kumar Sahu, R. Sithanandam , Anand Bulusu and Sudeb Dasgupta “TCAD Evaluation of Fin Architecture on SOI Substrate and its Comparison with Planar FDSOI MOSFET at 28nm Technology Node”,” VDAT, 2013.
  • Menka, Bulusu Anand and Dasgupta S., “A TCAD approach to evaluate channel electrondensity of double gate symmetric n-tunnel FET”, INDICON 2012, pp:577-581.
  • Baljit Kaur, S. Miryala, S. K. Manhas and Bulusu Anand, “An Efficient Method for ECSM Characterization of CMOS Inverter in Nanometer Range Technologies,” Accepted in IEEE International Symposium on Quality Electronic Design (ISQED) 2013.
  • Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, Bulusu Anand, “Underlap FinFET Capacitance: Impact of Input Transition Time and Output Load” IEEE International Nanoelectronics Conference (INEC) 2013.
  • Alam, B. Anand, and S. Dasgupta, “Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance”, in IEEE ISQED, 2012, pp. 717-720.
  • Alam, B. Anand, and S. Dasgupta, “Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance”, in VDAT 2012, pp. 357-359.
  • Alam, S. Dasgupta, and B. Anand “Impact of process-induced mechanical stress on multi-fingered device performance”, in Proc. IWPSD, 2011.
  • Arnab Kumar Biswas, Anand Bulusu and Sudeb Dasgupta, “A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz,” Proceedings of IEEE ISVLSI 2011.
  • Sandeep Miryala, Baljit Kaur, Bulusu Anand and Sanjeev Manhas, “Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model,” Proceedings of IEEE ISQED 2011.
  • Saurabh Nema, Mayank Srivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, “A Novel Scaling Strategy for Underlap FinFETs,” ICCCD 2010, IIT Kharagpur.
  • Bulusu Anand, V. Ramgopal Rao and M. P. Desai, “Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics,” Accepted in VLSI-DAT, 2007.
  • Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, “Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits”, Proceedings of 35th International Conference on Solid State Devices and Materials (SSDM 2004), pp. 434-435, Tokyo, Japan, September 15-17, 2004.
  • Sushant Suryagandh, B. Anand, M. P. Desai and V. Ramgopal Rao, “Dynamic Threshold Voltage CMOS (DTMOS) for Future Low Power Sub-1V Applications,” Proceedings of 10th International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 655-658, December 1999, New Delhi.

IP:

  • Bulusu Anand, Shivananda Reddy, Surya Veeraraghavan, “A Method to Find Sensitivity of Standard Cells to Process/Model Changes,” Defensive Publication of Freescale Semiconductor Inc., June 2008, http://www.priorartdatabase.com/IPCOM/000172383/
  • K. Manhas, S. Nema, A. Bulusu, “A method of fabricating dual/asymmetric dielectric constant (dual-K) spacers in MOSFET,” application no. CINIITR000100017, 2012 (Provisional Indian Patent).
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