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Introduction

The Device Research Lab, or DiRac Lab in short, is the hub of all research activities related to semiconductor devices in the department of Electronics and Communication Engineering, IIT Roorkee. The DiRac lab is a part of the CiDeR group, ECE, IIT Roorkee. We work on all aspects of semiconductor devices starting from material physics through device design and modeling, all the way to device-circuit co-design for a wide variety of applications. This website will provide a glimpse into the scope of our work, our ongoing projects as well as current and past members. Check the Announcement section for the latest updates and information regarding all available research positions.

News

  • We are working with the University of California Berkeley on Machine Learning augmented EDA development.

  • Prof. Avirup Dasgupta has won the IEEE EDS Early Career Award 2021. This is one of the highest awards in the field of Electron Devices, which is awarded to only one or two researchers worldwide per year. This year, he shares the award with Dr. Jiaju Ma.

  • Our group is working with Intel and GlobalFoundries on exploratory topics in Non-Volatile Memory for Artificial Intelligence.

  • Our group is now a part of the BSIM group (UC Berkeley) and the Berkeley Device Modeling Center (BDMC, UC Berkeley).

  • BSIM-CMG 111.1.0 becomes the first industry standard compact model for GAAFETs/Nanosheets.

  • The Industry standard ASM-HEMT Model is now available in EDA tools - AWR Microwave Office, AMCAD-IVCAD, Keysight (Parameter Extraction Video), Silvaco SmartSpice and Utmost IV.

Announcements

  • Looking for highly motivated postdoctoral scholars with a background in semiconductor devices. Prior experience with TCAD and SPICE simulations is essential. Knowledge of compact/SPICE modeling and related tools (like Keysight ICCAP) preferred. Interested candidates can send their CV to diraclab@ece.iitr.ac.in (cc: avirup@ece.iitr.ac.in)

  • Open positions are available for Ph.D. candidates, M.Tech candidates and various short-term research positions. Sincere and motivated candidates can send their CV to diraclab@ece.iitr.ac.in (cc: avirup@ece.iitr.ac.in)

Collaborations




People

Faculty:

Prof. Avirup Dasgupta

Research area: Compact (SPICE) modeling of semiconductor devices, semiconductor device physics, modeling and simulation
Email: avirup@ece.iitr.in
Phone: (+91-1331)-284967 [Office]

Prof. Tanmoy Pramanik

Research area: Non-volatile memories, neuromorphic hardware, memory reliability
Email: pramanik.tanmoy@ece.iitr.ac.in
Phone: (+91-1332)28- [Office]

Prof. Sourajeet Roy

Research area: Machine learning based EDA, numerical modeling and simulation of high speed devices and circuits
Email: sourajeet.roy@ece.iitr.ac.in
Phone: (+91-1332)28-5762 [Office]

Prof. Sudeb Dasgupta

Research area: Low power design, nanoscale device modeling, radiation hardened ICs and devices
Email: sudeb.dasgupta@ece.iitr.ac.in
Phone: (+91-1332)28-5666 [Office]

Prof. Anand Bulusu

Research area: Circuit design, circuit performance models and design, device-circuit codesign
Email: anand.bulusu@ece.iitr.ac.in
Phone: (+91-1332)24-6588 [Office]

Postdoc:

S. Manikandan

Research area: Gate-All-Around FETs
Supervisor(s): Sudeb Dasgupta

Rahul Kumar

Research area: Machine learning enhanced device modeling
Supervisor(s): Sourajeet Roy

Ph.D.:

Anirban Chowdhury

Research area: Gate-All-Around FETs
Supervisor(s): Avirup Dasgupta

Abhishek Kumar

Research area: Ferroelectric FETs
Supervisor(s): Avirup Dasgupta, Anand Bulusu, Shruti Mehrotra (GF)

Swapna Sarker

Research area: Semiconductor devices
Supervisor(s): Avirup Dasgupta

Mundhe Pratiksha Keshav

Research area: MRAM – devices, circuits and applications
Supervisor(s): Tanmoy Pramanik

Surila Guglani

Research area: Stochastic modeling, machine learning for EDA
Supervisor(s): Sourajeet Roy

M.Tech:

Upadesh Kumar

Research area: Compact modeling of STT-MRAM devices
Supervisor(s): Avirup Dasgupta

Shreyas Jitendra Tembhre

Research area: Spin-orbit torque magnetic random-access memory
Supervisor(s): Tanmoy Pramanik

B.Tech:

Arpit Mangal

Research area: Partitioning schemes in advanced semiconductor FETs
Supervisor(s): Avirup Dasgupta

Rohit Kumar

Research area: Partitioning schemes in advanced semiconductor FETs
Supervisor(s): Avirup Dasgupta

Motam Shiva Teja

Research area: Numerical modeling of switching dynamics of scaled MRAM cell
Supervisor(s): Avirup Dasgupta and Tanmoy Pramanik

Sourabh Singh

Research area: Numerical modeling of switching dynamics of scaled MRAM cell
Supervisor(s): Avirup Dasgupta and Tanmoy Pramanik

Harshvardhan

Research area: Modeling stochastic switching in magnetic memories
Supervisor(s): Avirup Dasgupta and Tanmoy Pramanik

Gurpreet Singh

Research area: Modeling stochastic switching in magnetic memories
Supervisor(s): Avirup Dasgupta and Tanmoy Pramanik

Mehul Arya

Research area: Self-heating in STT-MRAMs
Supervisor(s): Avirup Dasgupta

Jitendra Patel

Research area: SPICE model for STT-MRAMs
Supervisor(s): Avirup Dasgupta

Research intern:

Daaris Ameen

Research area: Semiconductor devices
Supervisor(s): Avirup Dasgupta

Adrija Mukherjee

Research area: Compact modeling of FeFETs
Supervisor(s): Avirup Dasgupta

Alumni:

S.No. Name Position Duration Current affiliation
1. Tanmay Joshi Research Intern Summer 2021 IIIT Bengaluru



Research

Ongoing sponsored projects:

Funding Agency Topic PI Co-PI Budget (INR) Duration
Science and Engineering Research Board, Govt. of India Development and Optimization of Magnetic Field Tolerant Spintronic Devices Targeted Toward Mobile and IOT Applications Tanmoy Pramanik -- 31.5 Lakhs 2021-2023
Science and Engineering Research Board, Govt. of India Variability Aware Compact Modeling of Nanosheet FETs Avirup Dasgupta -- 29.9 Lakhs 2021-2023
Berkeley Device Modeling Center (BDMC) Compact modeling of advanced semiconductor devices Avirup Dasgupta -- 15 Lakhs 2021-2022 (renewed yearly)
Qualcomm India (Qualcomm Innovation Fellowship India 2021) Fast Machine Learning Based Parametric SPICE Macromodel Extraction for FinFET Device-to-System Level Optimization Sourajeet Roy Sudeb Dasgupta 10 Lakhs 2021-2022
Indian Institute of Technology Roorkee Modeling and simulation of stacked Nanosheet FETs for upcoming technology nodes Avirup Dasgupta -- 20 Lakhs 2021-2023
Indian Institute of Technology Roorkee DiRac Lab Development ECE -- 30.9 Lakhs 2021-2022
Grand total 1.37 Crores
*Some sponsored projects are not listed due to existing confidentiality agreements.


Ongoing collaborations:

Collaborator Topic
Berkeley Device Modeling Center (BDMC), UC Berkeley Compact modeling of advanced semiconductor devices
BSIM group, UC Berkeley Research for BSIM models
Intel Corp. Non-volatile memory**
GlobalFoundries Engg. Pvt. Ltd. Non-volatile memory**
Nanolab, IIT Kanpur Modeling of semiconductor devices
IIT Jodhpur Compact modeling of STT-MRAM devices
Silvaco Inc., and Nanolab, IIT Kanpur Modeling of phase-transition materials
Politecnico di Torino, Italy Machine learning approaches for device modeling
IIT Ropar Machine learning for graphene interconnects at sub 22nm
*Some sponsored projects are not listed due to existing confidentiality agreements.
**Complete details of projects cannot be disclosed due to existing confidentiality agreements.

Publications

2021:

Journal:

  1. G. Pahwa, P. Kushwaha, A. Dasgupta, S. Salahuddin and C. Hu, “Compact Modeling of Temperature Effects in Modern MOSFETs down to Cryogenic Temperatures”, IEEE Transactions on Electron Devices, Vol. 68, Issue 9, 2021.
  2. M.-Y. Kao, Y.-H. Liao, G. Pahwa, A. Dasgupta, S. Salahuddin and C. Hu, “Energy Storage and Reuse in Negative Capacitance”, IEEE Transactions on Electron Devices, Vol. 68, Issue 4, 2021.
  3. U. Roy, T. Pramanik, S. Roy, A. Chatterjee, L. F. Register and S. K. Banerjee, “Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory”, ACM Transactions on Design Automation of Electronic Systems, Vol. 26, Issue 3, 2021.
  4. A. Jadhav, T. Ozawa, A. Baratov, J. T. Asubar, M. Kuzuhara, A. Wakejima, S. Yamashita, M. Deki, Y. Honda, S. Roy, H. Amano, B. Sarkar, “Generalized frequency dependent small signal model for high frequency analysis of AlGaN/GaN MOS-HEMTs,” IEEE Journal of Electron Devices Society, vol. 9, 2021

Conference:

  1. A. Dasgupta, "BSIM-CMG: Compact Model for Gate-All-Around FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2021. (Invited)
  2. R. Kumar, S. Sarker, S. Dasgupta, A. Dasgupta, S. Roy, "Fast extraction of quantum confinement effect on threshold voltage of Gate-All-Around FETs using machine learning methods", International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2021.
  3. S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Dasgupta, A. Bulusu, "Analysis of Self-Heating in 5nm Stacked Nanosheet Transistor", International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2021.
  4. A. Dasgupta, "Compact Modeling for Gate-All-Around FET Technology", MOS-AK (Asia Pacific) Workshop, 2021.(Invited)
  5. Y-F Chang, I. Karpov, R. Hopkins, D. Janosky, J. Medeiros, B. Sherrill, J. Zhang, Y. Huang, T. Pramanik, A. Chen, T. Acosta, A. Guler, J. A. O'Donnell, P. A. Quintero, N. Strutt, O. Golonzka, C. Connor, J. C. Lee and J. Hicks, “Embedded emerging memory technologies for neuromorphic computing: temperature instability and reliability”, IEEE International Reliability Physics Symposium (IRPS), 2021.

Invited Talks:

  1. A. Dasgupta, "BSIM-CMG: Compact Model for Gate-All-Around FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), IIT Delhi, Dec. 2021.
  2. A. Dasgupta, "Compact Modeling for Gate-All-Around FET Technology", MOS-AK (Asia Pacific) Workshop, Feb. 2021.
  3. A. Dasgupta, "Design and Modeling of Nanosheet FETs", IITK Short Course, Feb. 2021.
  4. A. Dasgupta, "Design Considerations and Compact Modeling of GAAFETs for Upcoming Technology Nodes", AICTE Workshop, NIT Meghalaya, Feb. 2021. (Keynote)
  5. S. Roy and R. Sharma, “Implications of Thermal Aspects on Interconnect and Packaging Technology - An Electro-Thermal Co-Design Perspective” in IEEE Electrical Design of Advanced Packaging and Systems Conference, Virtual Conference, December 14th, 2020
  6. S. Roy, “Recent Advances in Statistical Machine Learning for Uncertainty Quantification of High-Speed Circuits” in Workshop on Next Generation Electronic Systems: Heterogeneous Integration, Thermal and Power Management, Related Machine Learning organized by Binghamton University, SUNY, New York, October 8th, 2020
  7. S. Roy and R. Sharma, “Graphene-Based Emerging Interconnects - From Physics-Based Deterministic SPICE Models to Uncertainty Quantification” in IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, October 7th, 2020
  8. R. Sharma and S. Roy, “Understanding the Impact of Surface Roughness on the Performance of Next Generation Cu Interconnects” in IEEE Electrical Design of Advanced Packaging and Systems Conference, Kaohsiung, Taiwan, December 14th, 2019