diraclab@ece.iitr.ac.in
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Introduction

The Device Research Lab, or DiRac Lab in short, is the hub of all research activities related to semiconductor devices in the department of Electronics and Communication Engineering, IIT Roorkee. We work on all aspects of semiconductor devices starting from material physics through device design and modeling, all the way to device-circuit co-design for a wide variety of applications. This website will provide a glimpse into the scope of our work, our ongoing projects as well as current and past members. Check the Announcement section for the latest updates and information regarding all available research positions.

News

  • We are working with Lancaster University on novel memory devices

  • We are working with Semiconductor Research Corporation on Machine Learning augmented Compact Models

  • We are working with the University of California Berkeley on Machine Learning augmented EDA development.

  • Our group is working with GlobalFoundries on exploratory topics in Non-Volatile Memory and Machine Learning.

  • BSIM-CMG 111.1.0 becomes the first industry standard compact model for GAAFETs/Nanosheets.
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Announcements

  • Open positions for ph.D. candidates will be available soon.

Collaborations

IIT Kanpur
IIT Ropar
Polytechnico di Torino




People

Faculty:

Prof. Avirup Dasgupta

Research area: Compact (SPICE) modeling of semiconductor devices, semiconductor device physics and modeling
Email: avirup@ece.iitr.in
Phone: (+91-1331)-284967 [Office]

Prof. Tanmoy Pramanik

Research area: Non-volatile memories, neuromorphic hardware, memory reliability
Email: pramanik.tanmoy@ece.iitr.ac.in
Phone: (+91-1332)28- [Office]

Prof. Sourajeet Roy

Research area: Machine learning based EDA, numerical modeling and simulation of high speed devices and circuits
Email: sourajeet.roy@ece.iitr.ac.in
Phone: (+91-1332)28-5762 [Office]

Prof. Sudeb Dasgupta

Research area: Low power design, nanoscale device modeling, radiation hardened ICs and devices
Email: sudeb.dasgupta@ece.iitr.ac.in
Phone: (+91-1332)28-5666 [Office]

Prof. Anand Bulusu

Research area: Circuit design, circuit performance models and design, device-circuit codesign
Email: anand.bulusu@ece.iitr.ac.in
Phone: (+91-1332)24-6588 [Office]

Postdoc:

Mohammad Ehteshamuddin

Research area: RF performance of semiconductor devices
Supervisor(s): Avirup Dasgupta

Ankur Garg

Research area: Novel semiconductor materials and devices
Supervisor(s): Avirup Dasgupta

Ph.D.:

Surila Guglani

Research area: Stochastic modeling, machine learning for EDA
Supervisor(s): Sourajeet Roy

Jyoti Patel

Research area: Semiconductor device physics and modeling
Supervisor(s): Sudeb Dasgupta

Abhishek Kumar

Research area: Ferroelectric FETs
Supervisor(s): Avirup Dasgupta, Anand Bulusu, Shruti Mehrotra (GF)

Swapna Sarker

Research area: Semiconductor devices
Supervisor(s): Avirup Dasgupta

Kumar Sheelvardhan

Research area: Semiconductor device physics and modeling
Supervisor(s): Avirup Dasgupta

Sonalie Ahirwar

Research area: Materials and device: growth, characterization and modeling
Supervisor(s): Tanmoy Pramanik

Mohit Shukla

Research area: Modeling of semiconductor devices
Supervisor(s): Avirup Dasgupta

Prabhat Ranjan

Research area: 2D materials
Supervisor(s): Avirup Dasgupta, Amit Agarwal (Phy, IITK)

Srishti

Research area: Semiconductor device modeling
Supervisor(s): Avirup Dasgupta

Anamika Singh

Research area: Semiconductor device modeling
Supervisor(s): Avirup Dasgupta

Guntas Kaur

Research area: Magnetic materials and devices
Supervisor(s): Tanmoy Pramanik

Shusheel Kumar Arya

Research area: Magnetic materials and devices
Supervisor(s): Tanmoy Pramanik

M.Tech:

Abhinav Srivastava

Research area: Ultra-thin semiconductors
Supervisor(s): Avirup Dasgupta

Gitesh Gaharwar

Research area: Machine learning for EDA
Supervisor(s): Avirup Dasgupta

Arun Saxena

Research area: Memory devices
Supervisor(s): Avirup Dasgupta

Vaibhav Saini

Research area: TBD
Supervisor(s): Avirup Dasgupta

B.Tech:

Sneha Jain

Research area: Modeling of semiconductor devices
Supervisor(s): Avirup Dasgupta
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Research

Ongoing sponsored projects:

Funding Agency Topic PI Co-PI Budget (INR) Duration
Semiconductor Research Corportaion (SRC) Machine Learning augmented SPICE Models for Efficient Circuit Design Avirup Dasgupta Sourajeet Roy 34.8 Lakhs 2022-2025
IEEE EDS Machine Learning for Electron Devices (Summer school) Avirup Dasgupta 7.7 Lakhs 2022-2023
SMILE, IIT Roorkee THz Characterization System N. Pathak, D. Singh, A. Patnaik, A. Kumar Sah, E. Sharma, M. Rawat, A. Bulusu, B. P. Das, S. Roy, B. Sarkar, S. Dasgupta, S. Kumar, K. Rawat, R. Panigrahi, U. Dey, Gowrish B., A. Dasgupta, D. Bhatt, R. Kumar, A. Samanta, R. Sharma 650 Lakhs --
Indian Institute of Technology Roorkee Materials and devices for emerging anti-ferromagnetic memories Tanmoy Pramanik -- 20 Lakhs 2022-2024
Indian Institute of Technology Roorkee Analysis and Modeling of Ultra-thin Semiconductors for Future Technology Nodes Avirup Dasgupta -- 21.9 Lakhs 2022-2025
Science and Engineering Research Board, Govt. of India Development and Optimization of Magnetic Field Tolerant Spintronic Devices Targeted Toward Mobile and IOT Applications Tanmoy Pramanik -- 31.5 Lakhs 2021-2023
Indian Institute of Technology Roorkee Matching Grant: Variability Aware Compact Modeling of Nanosheet FETs Avirup Dasgupta -- 9.5 Lakhs 2021-2023
Science and Engineering Research Board, Govt. of India Variability Aware Compact Modeling of Nanosheet FETs Avirup Dasgupta -- 31.6 Lakhs 2021-2023
Berkeley Device Modeling Center (BDMC) Compact modeling of advanced semiconductor devices Avirup Dasgupta -- 92 Lakhs 2021-2026
Qualcomm India (Qualcomm Innovation Fellowship India 2021) Fast Machine Learning Based Parametric SPICE Macromodel Extraction for FinFET Device-to-System Level Optimization Sourajeet Roy Sudeb Dasgupta 10 Lakhs 2021-2022
Indian Institute of Technology Roorkee Modeling and simulation of stacked Nanosheet FETs for upcoming technology nodes Avirup Dasgupta -- 20 Lakhs 2021-2023
Indian Institute of Technology Roorkee DiRac Lab Development ECE -- 30.9 Lakhs 2021-2022
Grand total 9.52 Crores
*Some sponsored projects are not listed due to existing confidentiality agreements.


Ongoing research collaborations:

Collaborator Topic
Ecole Polytechnique Federale de Lausanne (EPFL) Ferroelectric devices
Semiconductor Research Corporation Machine Learning augmented compact modeling
Berkeley Device Modeling Center (BDMC), UC Berkeley Compact modeling of advanced semiconductor devices
BSIM group, UC Berkeley Research for BSIM models
University of Glasgow Modeling and simulation of advanced semiconductor technologies
GlobalFoundries Engg. Pvt. Ltd. Non-volatile memory**, Machine Learning**
Lancaster University Novel memory devices
Politecnico di Torino, Italy Machine learning approaches for device modeling
QTT group, IIT Kanpur Simulation of 2D materials and devices
Nanolab, IIT Kanpur Modeling of semiconductor devices
Silvaco Inc., and Nanolab, IIT Kanpur Modeling of phase-transition materials
IIT Ropar 2D materials and interconnects
*Some sponsored projects are not listed due to existing confidentiality agreements.
**Complete details of projects cannot be disclosed due to existing confidentiality agreements.

Publications

2023:

Journal:

  1. K. Sheelvardhan, S. Guglani, M. Ehteshamuddin, S. Roy and A. Dasgupta, "Machine Learning Augmented Compact Modeling for Simultaneous Improvement in Computational Speed and Accuracy", accepted, IEEE Transactions on Electron Devices, 2023.

Conference:

  1. M. Yusuf, S. Singh, B. Sarkar, A. Dasgupta and S. Roy, "A Deep Learning Space Mapping based Enhancement of Compact Models for Accurate Prediction of Trapping in GaN HEMTs from DC to mm-Wave Frequency", International Microwave Symposium (IMS), San Diego, CA, 2023.
  2. K. Sheelvardhan, S. Guglani, M. Ehteshamuddin, S. Roy and A. Dasgupta, "Variability Aware FET Model with Physics Knowledge Based Machine Learning", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Seoul, Korea, Mar. 2023
  3. S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Dasgupta and A. Bulusu, "A New Insight into the Saturation Phenomenon in Nanosheet Transistor: A Device Optimization Perspective", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Seoul, Korea, Mar. 2023.

Invited Talks:

  1. A. Dasgupta, "Machine Learningfor Semiconductor Devices", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  2. S. Roy, "Machine learning techniques as alternative to physical models for parametric sweeps", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  3. A. Kumar, "Ferroelectric devices for advanced memory technologies", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  4. M. Shukla, "Partitioning of charges in MOSFETs", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  5. M. Ehteshamuddin, "Design and optimization of emerging semiconductor devices", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  6. P. Ranjan, "Absorption enhancement in 2D material for emerging semiconductor applications", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  7. S. Sarker, "Compact modeling of emerging FETs for future technology nodes", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.
  8. K. Sheelvardhan, "Variability aware FET model with physics knowledge based machine learning", IEEE EDS Workshop on Devices and Circuits (WDC), Khajuraho, India, Jan. 2023.

2022:

Journal:

  1. R. Kumar, S. S. Likith Narayan, S. Kumar, S. Roy, B. K. Kaushik, R. Achar, and R. Sharma, “Knowledge based neural networks for fast design space exploration of hybrid copper-graphene on-chip interconnect networks,” IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 1, 2022.
  2. A. Jadhav, T. Ozawa, A. Baratov, J. T. Asubar, M. Kuzuhara, A. Wakejima, S. Yamashita, M. Deki, S. Nitta, Y. Honda, H. Amano, S. Roy, B. Sarkar, “An accurate approach to develop small signal circuit models for AlGaN/GaN HEMTs using rational functions and dependent current sources,” IEEE Journal of Electron Devices Society, vol. 10, Issue 7, 2022.
  3. S. Kushwaha, N. Soleimani, F. Trevisio, R. Kumar, R. Trinchero, F. G. Canavero, S. Roy, and R. Sharma, “Comparative analysis of prior knowledge-based machine learning metamodels for modeling hybrid copper-graphene on-chip interconnects,” IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 6, 2022.
  4. S. Guglani, Km. Dimple, S. Roy, R. Sharma, and B. K. Kaushik, “A bilevel multi-fidelity polynomial chaos approach for the uncertainty quantification of MWCNT interconnect networks with variable imperfect contact resistances,” IEEE Access, vol. 10, 2022.
  5. A. Pon, M. Ehteshamuddin, K. Sheelvardhan and A. Dasgupta, "Analysis of 1/f and G-R Noise in Phosphorene FETs", Solid State Electronics, Vol. 200(108530), 2022.
  6. N. Mishra, B. Pandey, V. Tomar, A. Dasgupta and S. Kumar, "Investigating the Infrared (IR) Absorption and Optoelectronic Properties of Mn-doped MoSe2 ML by Adsorption of NOx Gas Molecules", IEEE Sensors Journal, Vol. 22, Issue 23, 2022.
  7. A. Roy, T. Pramanik, S. Chowdhury, and S. K. Banerjee, "Phase-Field Modeling of Chemical Vapor-Deposited 2D MoSe2 Domains with Varying Morphology for Electronic Devices and Catalytic Applications", ACS Applied Nano Materials, accepted, 2022.

Conference:

  1. S. Ahirwar and T. Pramanik, "A Simulation Study of Stand-By and Active Write Mode Magnetic Immunity of Perpendicular Spin-Transfer-Torque Random-Access Memory", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec. 2022.
  2. S. Parandiyal, A. Singh, K. Sheelvardhan, S. Guglani, M. Ehteshamuddin, S. Roy and A. Dasgupta, "An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec. 2022.
  3. A. Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra and A. Dasgupta, "Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec. 2022.
  4. M. Subramaniyan, N. Chauhan, N. Bagga, A. Kumar, S. K. Banchhor, S. Roy, A. Dasgupta, A. Bulusu and S. Dasgupta, "Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec. 2022.
  5. G. Pahwa, A. Dasgupta, C. T. Tung, M.Y. Kao, C. K. Dabhi, S. Sarker, S. Salahuddin and C. Hu, "Compact Modeling of Emerging IC Devices for Technology-Design Co-development", IEEE International Electron Devices Meeting (IEDM), San Francisco, 2022. (Invited)
  6. S. Guglani, Km Dimple, A. Dasgupta, R. Sharma, B. K. Kaushik and S. Roy, "A Transfer Learning Approach to Expedite Training of Artificial Neural Networks for Variability-Aware Signal Integrity Analysis of MWCNT Interconnects ", IEEE Electrical Performance Electronic Packaging Systems Conference (EPEPS), San Jose, CA, USA, Oct. 2022.
  7. A. Pon, M. Ehteshamuddin, K. Sheelvardhan, and A. Dasgupta, "Analysis of 1/f and G-R Noise in Phosphorene FETs", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Granada, Spain, Sep. 2022.
  8. S. Guglani, J. Patel, A. Dasgupta, M.-Y. Kao, C. Hu, S. Roy, "Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs", Device Research Conference (DRC), Ohio, USA, June 2022.
  9. A. Kar, S. Sarker, A. Dasgupta, and Y. S. Chauhan, "Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes", Device Research Conference (DRC), Ohio, USA, June 2022.
  10. N. Chauhan, C. Garg, K. Ni, A. K. Behera, S. Yadav, S. K. Banchhor, N. Bagga, A. Dasgupta, A. Dutta, S. Dasgupta, A. Bulusu, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI", IEEE International Reliability Physics Symposium (IRPS), Dallas, 2022.
  11. J. Patel, S. Banchor, S. Guglani, A. Dasgupta, S. Roy, A. Bulusu and S. Dasgupta, "Design Optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-FinFET for Mid-Band 5G Application", International Conference on VLSI Design, Feb. 2022.

Invited Talks:

  1. S. Roy, "Machine Learning Techniques as Alternative to Physics Based Parametric Device Model Development", IEEE Internationcal Conference on Emerging Electronics (ICEE), Bengaluru, India, 2022.
  2. T. Pramanik, "Uncovering stochastic write-error problems in STT-MRAM using micromagnetic modeling", IEEE Internationcal Conference on Emerging Electronics (ICEE), Bengaluru, India, 2022.
  3. A. Dasgupta, "BSIM: A family of Industry Standard Compact Models for Modern FETs", IEEE Internationcal Conference on Emerging Electronics (ICEE), Bengaluru, India, 2022.
  4. A. Dasgupta, "Machine Learning for Semiconductor Devices", Research Opportunities in Semiconductor Materials and Devices (ROSMD), Oct. 2022.
  5. A. Dasgupta, "Recent Developments in Compact Models for Multi-Gate FETs", IEEE EDS Workshop on Devices and Circuits (WDC), Goa, Mar. 2022.
  6. S. Roy, "Machine Learning and Its Opportunities in Device Modeling and Simulation", IEEE EDS Workshop on Devices and Circuits (WDC,) Goa, Mar. 2022.
  7. S. Sarker, "ML Augmented Compact Model of Subband Energy for GAAFETs", IEEE EDS Workshop on Devices and Circuits (WDC), Goa, Mar. 2022.
  8. S. Guglani, "Machine learning based Surrogate Models for Device Modeling", IEEE EDS Workshop on Devices and Circuits (WDC), Goa, Mar. 2022.
  9. J. Patel, "FinFET Technology for Mid-Band 5G Application", IEEE EDS Workshop on Devices and Circuits (WDC), Goa, Mar. 2022.
  10. A. Dasgupta, "Recent developments in compact models for modern and future technologies", Chandigarh University, Mar. 2022.
  11. A. Dasgupta, "BSIM compact models for present and future Multi-Gate FETs", Micron Technology, Inc., Mar. 2022.

2021:

Journal:

  1. G. Pahwa, P. Kushwaha, A. Dasgupta, S. Salahuddin and C. Hu, “Compact Modeling of Temperature Effects in Modern MOSFETs down to Cryogenic Temperatures”, IEEE Transactions on Electron Devices, Vol. 68, Issue 9, 2021.
  2. M.-Y. Kao, Y.-H. Liao, G. Pahwa, A. Dasgupta, S. Salahuddin and C. Hu, “Energy Storage and Reuse in Negative Capacitance", IEEE Transactions on Electron Devices, Vol. 68, Issue 4, 2021.
  3. U. Roy, T. Pramanik, S. Roy, A. Chatterjee, L. F. Register and S. K. Banerjee, “Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory”, ACM Transactions on Design Automation of Electronic Systems, Vol. 26, Issue 3, 2021.
  4. A. Jadhav, T. Ozawa, A. Baratov, J. T. Asubar, M. Kuzuhara, A. Wakejima, S. Yamashita, M. Deki, Y. Honda, S. Roy, H. Amano, B. Sarkar, “Generalized frequency dependent small signal model for high frequency analysis of AlGaN/GaN MOS-HEMTs”, IEEE Journal of Electron Devices Society, vol. 9, 2021

Conference:

  1. A. Dasgupta, "BSIM-CMG: Compact Model for Gate-All-Around FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2021. (Invited)
  2. R. Kumar, S. Sarker, S. Dasgupta, A. Dasgupta, S. Roy, "Fast extraction of quantum confinement effect on threshold voltage of Gate-All-Around FETs using machine learning methods", International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2021.
  3. S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Dasgupta, A. Bulusu, "Analysis of Self-Heating in 5nm Stacked Nanosheet Transistor", International Workshop on Physics of Semiconductor Devices (IWPSD), Dec. 2021.
  4. A. Dasgupta, "Compact Modeling for Gate-All-Around FET Technology", MOS-AK (Asia Pacific) Workshop, 2021.(Invited)
  5. Y-F Chang, I. Karpov, R. Hopkins, D. Janosky, J. Medeiros, B. Sherrill, J. Zhang, Y. Huang, T. Pramanik, A. Chen, T. Acosta, A. Guler, J. A. O'Donnell, P. A. Quintero, N. Strutt, O. Golonzka, C. Connor, J. C. Lee and J. Hicks, “Embedded emerging memory technologies for neuromorphic computing: temperature instability and reliability”, IEEE International Reliability Physics Symposium (IRPS), 2021.

Invited Talks:

  1. A. Dasgupta, "BSIM-CMG: Compact Model for Gate-All-Around FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), IIT Delhi, Dec. 2021.
  2. A. Dasgupta, "Semiconductor devices: Recent advances and open problems", IEEE EDS Technical Talk, MSIT Kolkata, Oct. 2021.
  3. A. Dasgupta, "Design Considerations and Compact Modeling of GAAFETs for Upcoming Technology Nodes", Short Term Course on "Frontier Areas of Electronics and Communication Engineering: An Industry-Academia Convergence”, NIT-UK, Sep. 2021.
  4. A. Dasgupta, "Compact Modeling for Gate-All-Around FET Technology", MOS-AK (Asia Pacific) Workshop, Feb. 2021.
  5. A. Dasgupta, "Design and Modeling of Nanosheet FETs", IITK Short Course, Feb. 2021.
  6. A. Dasgupta, "Design Considerations and Compact Modeling of GAAFETs for Upcoming Technology Nodes", AICTE Workshop, NIT Meghalaya, Feb. 2021. (Keynote)
  7. S. Roy and R. Sharma, “Implications of Thermal Aspects on Interconnect and Packaging Technology - An Electro-Thermal Co-Design Perspective”, IEEE Electrical Design of Advanced Packaging and Systems Conference, December 14th, 2020
  8. S. Roy, “Recent Advances in Statistical Machine Learning for Uncertainty Quantification of High-Speed Circuits”, Workshop on Next Generation Electronic Systems: Heterogeneous Integration, Thermal and Power Management, Related Machine Learning organized by Binghamton University, SUNY, New York, October 8th, 2020
  9. S. Roy and R. Sharma, “Graphene-Based Emerging Interconnects - From Physics-Based Deterministic SPICE Models to Uncertainty Quantification”, IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, October 7th, 2020
  10. R. Sharma and S. Roy, “Understanding the Impact of Surface Roughness on the Performance of Next Generation Cu Interconnects”, IEEE Electrical Design of Advanced Packaging and Systems Conference, Kaohsiung, Taiwan, December 14th, 2019